Tech Director: Silicon Validation & Memory Interfaces

European Tech Recruit; Atlanta (GA); On-site; USD 180,000 - 260,000; Full time

Job summary

European Tech Recruit seeks a Technical Director Validation Engineer for memory interface silicon validation. The role centers on lab bring-up, data-driven validation, and the development of robust methodologies to ensure performance and specification compliance.

You will lead bench work, coordinate experiments with silicon design teams, and drive automation to accelerate test cycles across DDR topologies and high-speed interfaces. Strong leadership and deep EE expertise are essential.

Qualifications

• Requires a B.S./M.S. in Electrical Engineering and 20+ years of relevant experience.
• Experience bench-testing/high-speed I/O devices and memory interfaces.
• Proficiency with lab equipment (oscilloscopes, BERTs, signal generators) and test automation.

Responsibilities

• Lead lab bring-up and validation of high-speed memory buffer semiconductors.
• Develop test methodologies to validate silicon designs against specs.
• Develop scripts to automate lab equipment and data analysis.
• Lead validation activities from bench planning to execution and refinement.
• Collaborate with silicon design teams to drive experiments and data collection.
• Provide input into FPGA, system, and PCB design requirements.
• Support Applications teams in issue resolution with customers.
• Automate data collection and validation framework development.
• Work with processor-memory interfaces (DDR topologies/protocols).
• Apply high-speed signalling, SI, and PI concepts in validation.

Skills

Oscilloscopes

BERTs

Signal generators

Logic analyzers

Protocol analysers

Troubleshooting

High-speed I/O

Education

B.S. or M.S. in Electrical Engineering

Tools

ATE

System testing

PCB layouts

Job description

European Tech Recruit seeks a Technical Director Validation Engineer for memory interface silicon validation. The role centers on lab bring-up, data-driven validation, and the development of robust methodologies to ensure performance and specification compliance.

You will lead bench work, coordinate experiments with silicon design teams, and drive automation to accelerate test cycles across DDR topologies and high-speed interfaces. Strong leadership and deep EE expertise are essential.