Senior Verification Engineer, Networking ASICs

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Advanced Micro Devices, Inc. in Santa Clara, CA, is seeking a Design Verification Engineer to drive verification closure on complex ASIC designs. The ideal candidate will have robust knowledge of SystemVerilog and UVM, and experience in debugging intricate architecture issues.

This role involves developing UVM-based testbench architectures, collaborating with various teams, and optimizing verification plans. The company fosters a culture of innovation, making it a great place for career advancement.

Qualifications

• Expert-level knowledge of SystemVerilog and UVM.
• Strong debug skills across architecture, RTL, and testbench layers.
• Experience with industry protocols such as PCIe, AXI, and Ethernet.

Responsibilities

• Develop robust UVM-based testbench architectures for verification.
• Drive execution of verification plans and debug issues.
• Collaborate with cross-functional teams for high-quality deliverables.

Skills

SystemVerilog

UVM

Debugging

Scripting (Python)

Verifying complex IP

Knowledge of PCIe

Education

Bachelor's Degree in Electrical/Computer Engineering

Tools

VCS

Verdi/DVE

Waveform analysis tools

Job description

Advanced Micro Devices, Inc. in Santa Clara, CA, is seeking a Design Verification Engineer to drive verification closure on complex ASIC designs. The ideal candidate will have robust knowledge of SystemVerilog and UVM, and experience in debugging intricate architecture issues.

This role involves developing UVM-based testbench architectures, collaborating with various teams, and optimizing verification plans. The company fosters a culture of innovation, making it a great place for career advancement.