SystemC/TLM Performance Modeling Engineer

TPI Global Solutions

Santa Clara (CA)

On-site

USD 71,635 - 81,278

Full time

14 days+
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Job summary

A technology solutions provider is seeking a Performance Modeling / Verification Engineer to support system-level performance analysis for next-gen hardware platforms. You will develop high-fidelity performance models using SystemC and work closely with architecture and verification teams. Candidates should have 5+ years of SystemC experience, strong C++ skills, and a relevant degree in Electrical Engineering or Computer Science. This role is crucial for optimizing system designs and meeting performance targets.

Qualifications

  • 5+ years of recent hands-on SystemC experience.
  • Strong understanding of Transaction-Level Modeling (TLM / TLM2.0).
  • Proficiency in C++ programming.
  • Experience in performance modeling and system-level validation.
  • Exposure to verification concepts, including simulation and debugging.

Responsibilities

  • Develop, enhance, and maintain SystemC / TLM2 performance models.
  • Perform architecture exploration and performance analysis.
  • Identify system bottlenecks and optimize models.
  • Build and execute SystemC-based testbenches.
  • Collaborate with globally distributed engineering teams.

Skills

SystemC modeling experience
C++ programming skills
performance validation methodologies
architecture exploration
performance analysis

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Git
Perforce

Job description

A technology solutions provider is seeking a Performance Modeling / Verification Engineer to support system-level performance analysis for next-gen hardware platforms. You will develop high-fidelity performance models using SystemC and work closely with architecture and verification teams. Candidates should have 5+ years of SystemC experience, strong C++ skills, and a relevant degree in Electrical Engineering or Computer Science. This role is crucial for optimizing system designs and meeting performance targets.
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