CPU Architecture Performance Engineer — RTL & Modeling

Qualcomm; San Diego (CA); On-site; USD 148,300 - 222,500; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA is seeking a CPU Architecture Performance Engineer to lead verification for a world‑class mobile CPU.

You will verify performance features between RTL and models, troubleshoot issues, and collaborate with design and performance teams to create test cases and validate new features. The role requires CPU architecture expertise, RTL simulation experience, and strong C/C++/Verilog skills; MS/PhD prefered but multiple levels eligible.

Qualifications

• Proficiency in CPU architecture areas such as fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire, etc.
• Verify performance features between RTL and model and troubleshoot.
• Work with design and performance teams to develop test cases and validate new features.
• RTL simulation experience and performance modeling experience; proficiency in Verilog, C/C++ and scripting languages.

Responsibilities

• Lead performance verification for world‑class mobile/portable CPU.
• Verify performance features between RTL and model and troubleshoot as needed.
• Collaborate with design and performance teams to develop test cases and validate new features.

Skills

CPU architecture knowledge

RTL verification

Performance modeling

C/C++ programming

Verilog

Python scripting

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science

MS in Computer Architecture

PhD in Electrical/Computer Engineering or CS

Tools

Verilog

C/C++

Python

Perl

Job description

Qualcomm Technologies, Inc. in San Diego, CA is seeking a CPU Architecture Performance Engineer to lead verification for a world‑class mobile CPU.

You will verify performance features between RTL and models, troubleshoot issues, and collaborate with design and performance teams to create test cases and validate new features. The role requires CPU architecture expertise, RTL simulation experience, and strong C/C++/Verilog skills; MS/PhD prefered but multiple levels eligible.