Performance Modeling/Verification Engineer

Infobahn Softworld Inc; United States; On-site; USD 85,000 - 110,000; Part time

Job summary

A technology solutions provider in the United States is seeking a Performance Modeling/Verification Engineer to develop and enhance SystemC/TLM2 models for hardware components. The ideal candidate will have over 5 years of experience with SystemC, strong C++ skills, and be familiar with performance modeling techniques. This contract role involves collaborating with cross-functional teams and optimizing models for performance. Applicants should have a relevant degree and be ready to participate in system-level testing and debugging.

Qualifications

• Minimum 5 years of experience in SystemC.
• Proficiency in C/C++ programming.
• Knowledge of memory controller architectures, including DDR and LPDDR.
• Experience with handling complex projects.

Responsibilities

• Develop and maintain SystemC/TLM2 models for various hardware components.
• Collaborate with teams to integrate models into system-level designs.
• Optimize model performance to meet design specifications.
• Develop and execute testbenches for model validation.

Skills

SystemC

C++ integration

Transaction-Level Modeling

Verification methodologies

Debugging

Education

B.E/M.E/M.Tech or B.S/M.S in EE/CSE

Tools

SystemVerilog/UVM

Perforce

Git

Job description

Performance Modeling/Verification Engineer

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Minimum Requirements

• Minimum 5 years of experience in SystemC.
• Recent and relevant experience with SystemC.
• Familiarity with Transaction-Level Modeling (TLM) concepts and implementation.
• Experience in performance modeling and architecture exploration using SystemC.
• Ability to work with C++ integration, since SystemC is built on C++.
• Exposure to verification methodologies in SystemC (e.g., testbench creation, simulation).
• Knowledge of modeling at different abstraction levels (e.g., behavioral, RTL, TLM).

Job Duties

• Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.
• Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance.
• Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
• Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
• Create clear and comprehensive documentation for models, including usage guidelines and design specifications.

Deliverables

• Cycle approximate performance models
• SystemVerilog/UVM Functional and Performance Verification

Experience and Education

• B.E/M.E/M.Tech or B.S/M.S in EE/CSE with over 5 years of recent hands‑on experience in SystemC and TLM2 modeling
• Proficiency in C/C++ programming.
• Understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards is preferred.
• UVM verification experience is preferred.
• Experience with debuggers and handling complex projects.
• Experience working in geographically dispersed teams; must be a strong team player.
• Knowledge of system‑level architecture including buses like AXI/AHB and bridges is a plus.
• Familiarity with version control systems such as Perforce or Git

Seniority level

Mid-Senior level

Employment type

Contract

Industries

Semiconductor Manufacturing