Senior Software Engineer - Virtual Hardware Modeling

TALENT Software Services; Sunnyvale (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A technology consulting firm is seeking a Senior Software Engineer focused on Virtual Hardware Modeling. The ideal candidate will design and develop high-level models of complex SoC hardware, integrating various hardware accelerators. Applicants should have a B.S. in Computer Science or Electrical Engineering, along with 7-10 years of relevant experience in hardware simulation and modern C++. Proficiency in SystemC/TLM and experience with virtual platform tools are essential. This role offers a dynamic work environment and the opportunity to work on cutting-edge technology.

Qualifications

• 7-10+ years of experience in hardware model simulation and performance modeling.
• Experience in chip design and electronic design automation.
• Familiarity with standard C++ concurrency support library.

Responsibilities

• Design and develop SystemC TLM models for SoC architecture.
• Integrate models into the Virtual Platform and develop automated workflows.
• Collaborate with architects and engineers to develop high-fidelity models.
• Coordinate virtual platforms with hardware development programs.
• Enhance platforms for architecture exploration and performance metrics.

Skills

High proficiency in modern C++

Experience with SystemC/TLM library

Proficiency in Python

Familiarity with DSP architectures

Experience in hardware model simulation

Familiarity with NoC and cache modeling

Education

B.S. degree in Computer Science or Electrical Engineering

Tools

Synopsys Virtualizer

Cadence Virtual Platform

Imperas OVP

ARM Fast Models

Job description

Senior Software Engineer - Virtual Hardware Modeling

The compute performance and power efficiency requirements of custom AR/VR devices require custom silicon. Our client team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. We are seeking a modeling engineer to develop high‑level models of complex SoC hardware. This combines models of custom hardware accelerators for vision, 2D and 3D graphics, machine learning and more, within a multi‑core, multi‑level memory hierarchy SoC architecture, and serves as the primary simulation vehicle for system software and firmware.

Responsibilities

• Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network‑on‑Chip, DMA and memory controllers, etc.
• Integrate first‑party and vendor models into the Virtual Platform, develop automated workflows to ensure register‑level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration.
• Collaborate with silicon architects, digital designers and verification engineers to design and develop high‑fidelity, fast C++ models for first‑party IP.
• Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering, enabling end‑to‑end silicon validation test frameworks.
• Enhance the virtual platforms to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing for data‑driven design decisions and trade‑off analysis to optimize system performance and power consumption.

Minimum Qualifications

• B.S. degree in Computer Science or Electrical Engineering or equivalent experience.
• 7‑10+ years of experience with 5+ years experience in hardware model simulation, virtual platform, performance modeling of complex SoCs or high‑fidelity hardware accelerators.
• High proficiency in modern C++ in the domains of chip‑design, electronic design automation or simulation.
• Experience with the SystemC/TLM library.
• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models.
• Familiarity with processor/DSP architectures, such as ARM, RISC‑V, and XTensa.
• Familiarity with NoC, MMU, address translations, and cache modeling.
• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc.
• Proficiency in Python to automate design flows, creation of collateral data.