Performance Modeling Engineer for AI Accelerators and SoC

Qualcomm Technologies; Austin (TX); On-site; USD 192,000 - 288,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an experienced Performance Modeling Engineer to drive architectural exploration and system-level optimization for future processors, AI accelerators, and SoCs.

You will develop high-fidelity models, evaluate tradeoffs, and guide design decisions from concept through silicon. Applicants should have deep processor architecture knowledge, memory hierarchies, and TLM/SystemC expertise, with collaboration across RTL, verification, software, and system teams to

Qualifications

• BS/MS/PhD in Computer Engineering, Electrical Engineering, or Computer Science with 6+ years of related work experience.
• 10 years of industry experience in computer architecture, microarchitecture, or performance modeling.
• Deep knowledge of cache hierarchy, memory systems, SMP, and multicore scaling.

Responsibilities

• Develop and maintain transaction-level and analytical performance models for processors, memory hierarchies, interconnects, and accelerators.
• Create detailed models of cache hierarchies, coherent interconnects, memory subsystems, DMA engines, and SMP systems.
• Evaluate architectural tradeoffs in performance, power, area, latency, bandwidth, and scalability.
• Analyze workload behavior and identify system bottlenecks through simulation and modeling.
• Collaborate with hardware and software teams to correlate models with RTL simulations and silicon data.

Skills

Transaction-Level Modeling

C programming

Python programming

SystemC

Education

BS in Computer Engineering/Electrical Engineering/CS

MS in Computer Engineering/EE/CS

PhD in Computer Engineering/EE/CS

Tools

SystemC

Job description

Qualcomm Technologies, Inc. seeks an experienced Performance Modeling Engineer to drive architectural exploration and system-level optimization for future processors, AI accelerators, and SoCs.

You will develop high-fidelity models, evaluate tradeoffs, and guide design decisions from concept through silicon. Applicants should have deep processor architecture knowledge, memory hierarchies, and TLM/SystemC expertise, with collaboration across RTL, verification, software, and system teams to