Synthesis & Physical Design Engineer - High-Perf SoC

Nvidia Corporation in; Westford (MA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Physical Design Engineer specializing in Synthesis and Implementation to join the Networking Silicon team in the United States. You will own RTL-to-gate synthesis and QoR convergence for complex blocks, optimize flows, and collaborate across RTL, timing, and physical teams to deliver high-performance, low-latency chips.

Requirements include 2+ years in synthesis and physical implementation, scripting in Python/Perl/Tcl, and hands-on use of Fusion Compiler or Genus.

Qualifications

• BSEE, MSEE, or equivalent experience.
• 2+ years of experience in synthesis and physical implementation on advanced process nodes.
• Proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable synthesis tools.
• Hands-on experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow.
• Strong analytical and debugging skills across RTL, synthesis, timing, and physical implementation.
• Proficiency in Python, Perl, Tcl, and Make.
• Strong communication and multi-functional collaboration skills.

Responsibilities

• Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions.
• Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets.
• Analyze design bottlenecks and QoR regressions, collaborating with RTL, timing, architecture, and physical design teams to resolve them.
• Support physical implementation from floorplanning and power planning through routing and timing closure.
• Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies and best known methods.

Skills

Python

Perl

Tcl

Make

Strong communication

Education

BSEE

MSEE

Tools

Synopsys Fusion Compiler

Cadence Genus

Job description

NVIDIA is seeking a Physical Design Engineer specializing in Synthesis and Implementation to join the Networking Silicon team in the United States. You will own RTL-to-gate synthesis and QoR convergence for complex blocks, optimize flows, and collaborate across RTL, timing, and physical teams to deliver high-performance, low-latency chips.

Requirements include 2+ years in synthesis and physical implementation, scripting in Python/Perl/Tcl, and hands-on use of Fusion Compiler or Genus.