Static Timing Engineer for ASIC/FPGA (Onsite)

The Boeing Company; El Segundo (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

The Boeing Company in El Segundo, CA is seeking a Static Timing Analysis (STA) Engineer to join Boeing Space, Intelligence & Weapons Systems. You will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on critical programs across the Boeing Defense and Security enterprise.

You will collaborate with multiple electronics groups, train new engineers, and contribute to timing convergence across complex SoCs.

Qualifications

• Bachelor of Science required.
• Experience with static timing analysis (STA) workflows.
• Familiarity with ASIC/FPGA timing constraints and EDA tools.

Responsibilities

• Responsible for STA analysis and convergence throughout the ASIC cycle.
• Identify timing paths and constraints for digital, analog, and mixed-signal blocks.
• Collaborate with IP teams, EDA vendors, and foundries for design closure.
• Generate timing constraints for multiple ASICs and FPGAs.

Skills

Python

TCL

Perl

Unix shell

Education

Bachelor of Science

Job description

The Boeing Company in El Segundo, CA is seeking a Static Timing Analysis (STA) Engineer to join Boeing Space, Intelligence & Weapons Systems. You will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on critical programs across the Boeing Defense and Security enterprise.

You will collaborate with multiple electronics groups, train new engineers, and contribute to timing convergence across complex SoCs.