Senior ASIC/FPGA Digital Design Engineer

Boeing; El Segundo (CA); Hybrid; USD 146,000 - 223,000; Full time

Job summary

Boeing Space, Intelligence & Weapons Systems in California invites experienced ASIC/FPGA Digital Design Engineers (Lead or Senior) to join our Electronic Products team for aerospace projects in El Segundo or Huntington Beach. You will work on ASIC, FPGA, or mixed developments, covering RTL/HDL design, timing analysis, and verification collaboration.

We seek candidates with 9+ years in FPGA/ASIC/SoC design, strong HDL skills, and the ability to lead technical initiatives.

Qualifications

• BS degree in engineering or related field; 9+ years FPGA/ASIC/SoC design experience.
• Experience with HDL development, simulation, debug, and synthesis.
• Strong digital design fundamentals and timing basics.
• Experience debugging RTL/HDL and understanding CDC concepts.

Responsibilities

• Support ASIC, FPGA, or mixed ASIC/FPGA developments depending on assignment.
• Develop HDL/RTL for ASIC, FPGA, and SoC systems.
• Simulate, debug, and troubleshoot digital designs.
• Perform and/or support synthesis, constraints development, timing closure.
• Collaborate with verification teams for simulation and integration goals.
• Communicate technical status, risks, dependencies, and tradeoffs.

Skills

HDL development

RTL design

Simulation

Synthesis

Timing analysis

CDC concepts

Troubleshooting digital systems

Digital design fundamentals

Education

Bachelor’s degree in Engineering/EE/CS or related field

Master’s degree in EE/CS or related field

Tools

HDL tools

Synthesis tools

Simulation tools

Verification tools

Job description

Boeing Space, Intelligence & Weapons Systems in California invites experienced ASIC/FPGA Digital Design Engineers (Lead or Senior) to join our Electronic Products team for aerospace projects in El Segundo or Huntington Beach. You will work on ASIC, FPGA, or mixed developments, covering RTL/HDL design, timing analysis, and verification collaboration.

We seek candidates with 9+ years in FPGA/ASIC/SoC design, strong HDL skills, and the ability to lead technical initiatives.