Static Timing Analysis (STA) Engineer – (Lead or Senior)

The Boeing Company; El Segundo (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

The Boeing Company in El Segundo, CA is seeking a Static Timing Analysis (STA) Engineer to join Boeing Space, Intelligence & Weapons Systems. You will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on critical programs across the Boeing Defense and Security enterprise.

You will collaborate with multiple electronics groups, train new engineers, and contribute to timing convergence across complex SoCs.

Qualifications

• Bachelor of Science required.
• Experience with static timing analysis (STA) workflows.
• Familiarity with ASIC/FPGA timing constraints and EDA tools.

Responsibilities

• Responsible for STA analysis and convergence throughout the ASIC cycle.
• Identify timing paths and constraints for digital, analog, and mixed-signal blocks.
• Collaborate with IP teams, EDA vendors, and foundries for design closure.
• Generate timing constraints for multiple ASICs and FPGAs.

Skills

Python

TCL

Perl

Unix shell

Education

Bachelor of Science

Job description

Job Description

At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Static Timing Analysis (STA) Engineer to join us as part of our Boeing Electronic Products team located in El Segundo, CA and at the heart of Boeing’s products - ASICs and FPGAs.

Our Electronics Products team goal is to be Boeing’s sole source for electronics. We’ve grown by over 400% and continue to have new opportunities to support more Boeing Platforms. We are seeking an experienced Static Timing Analysis Engineer that is ambitious and will thrive in a technology development environment and can work the full spectrum from research through flight insertion.We’re highly supportive of innovative thinking, we respect and acknowledge hard work, we recognize maturity and integrity, and we reward bottom-line achievement. At Boeing, we value your curiosity, your determination, and your imagination. #TheFutureIsBuiltHere

The work we do enables the missions and needs of our customers as we help Connect, Protect, Explore, and Inspire the world. Our team of engineers leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world. We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. Plus, we're applying the latest digital IC design processes with industry-best tools to enable applications that cut across every domain at Boeing.

Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line – approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems).

As a Static Timing Analysis (STA) Engineer you will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on the most critical programs across the Boeing Defense and Security enterprise. You will collaborate with other electronics groups across the company and around the world from the early design stages until signoff to help achieve first pass success. You will be working with a large physical design team within the company and outside of the company for timing convergence. Boeing STA engineers are required work with IP team, EDA vendors, and Foundry for the design closure.

Position Responsibilities

• Responsible for STA analysis and convergence throughout the ASIC cycle

• Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)

• Facilitate STA methodology in collaboration with other STA leaders

• Generate timing constraints for multiple ASICs and FPGAs

• Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis

• Responsible for intricate cross domain timing path closure

• Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints

• Programming skills with Python, TCL, Perl, Unix shell etc.

• Help train new engineers

This position is expected to be 100% onsite. The selected candidate will be required to work onsite in El Segundo, CA.

Our worksite participates in Boeing’s optional 9/80 schedule rotation. 9/80 is a rotation in which employees can work 9-hour shifts, 8 days per pay period (bi-weekly) and receive every other Friday off.

Travel may be required up to 10% of the time; Domestically and/or internationally depending on business needs.

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.

Basic Qualifications (Required Skills/Experience)

• Bachelor of Science