ASIC STA Engineer: Timing Closure & IP Integration

Apple, Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple seeks an ASIC STA Engineer to lead timing closure across full chip and blocks, coordinating with SoC Design, Verification, DFT, Architecture and Physical Design teams. You will work with CAD/Flow teams to refine front-end timing methodologies and develop robust timing analysis flows.

The role requires a strong foundation in digital design and familiarization with Primetime, Synthesis, and timing concepts. You’ll be a self-motivated communicator driving cross-group collaboration.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 0+ years of experience acceptable; strong fundamentals required.
• Solid grounding in digital design and timing concepts.
• Proficient with TCL, Python and Perl scripting.
• Familiar with STA tools such as PrimeTime.
• Knowledge of front-end flows and methodologies.
• Self-motivated with good cross-team communication.

Responsibilities

• Own timing closure for full chip and block level timing.
• Collaborate with SoC Design, Verification, DFT, Architecture and Physical Design teams.
• Define and improve front-end timing methodologies with CAD/Flow teams.
• Develop and maintain timing analysis flows and methodologies.

Skills

Digital design

ASIC timing concepts

Scripting (TCL, Python, Perl)

Primetime STA

Front-end tools

Communication

Education

Bachelor's Degree

Tools

Primetime

Synthesis

DFT tools

Job description

Apple seeks an ASIC STA Engineer to lead timing closure across full chip and blocks, coordinating with SoC Design, Verification, DFT, Architecture and Physical Design teams. You will work with CAD/Flow teams to refine front-end timing methodologies and develop robust timing analysis flows.

The role requires a strong foundation in digital design and familiarization with Primetime, Synthesis, and timing concepts. You’ll be a self-motivated communicator driving cross-group collaboration.