Staff Timing Engineer – GPU IP Signoff & Convergence

Samsung Electronics America; Austin (TX); On-site; USD 151,000 - 227,000; Full time

Job summary

Samsung Electronics America is seeking a Staff Timing Engineer to join the GPU physical design team at the SARC/ACL center in Austin. The role focuses on timing integrity, signoff readiness, and power recovery for next‑generation GPU IPs used in premium smartphones and related markets.

You will collaborate with RTL, physical design, and EDA partners to drive timing closure across complex, multi-clock designs.

Qualifications

• 6+ years of ASIC timing experience or 4+ years with a Master’s degree or 2+ years with a Ph.D.
• Strong understanding of ASIC design flows and timing analysis fundamentals.
• Hands-on experience with industry STA tools (PrimeTime/Tempus).
• Familiarity with CTS, multi-voltage/multi-clock designs, UPF checks.

Responsibilities

• Perform top-level timing analysis and signoff readiness for GPU IPs.
• Develop timing constraints and budgets across multi-clock domains.
• Debug timing issues with RTL, physical design, and EDA partners.
• Contribute to timing convergence, model extraction, and power recovery.

Skills

ASIC timing analysis

Python scripting

Tcl scripting

Digital design

VLSI knowledge

Data-driven debugging

Education

Bachelor’s Degree in Computer Science/Engineering

Master’s Degree in Computer Science/Engineering

Ph.D. (optional)

Tools

PrimeTime

Tempus

CTS

UPF/Power intent tools

Job description

Samsung Electronics America is seeking a Staff Timing Engineer to join the GPU physical design team at the SARC/ACL center in Austin. The role focuses on timing integrity, signoff readiness, and power recovery for next‑generation GPU IPs used in premium smartphones and related markets.

You will collaborate with RTL, physical design, and EDA partners to drive timing closure across complex, multi-clock designs.