Senior GPU IP Physical Design Engineer

Samsung Semiconductor; Austin (TX); On-site; USD 151,000 - 227,000; Full time

Benefits offered by this job

401(k)

Tuition assistance

Paid time off

Wellness program

Onsite lunch

Job summary

Samsung Austin Research and Development Center (SARC/ACL) seeks a Senior or Staff Physical Design Engineer to drive physical implementation of GPU IP, impacting power, performance and area across advanced process nodes.

You will execute floorplanning, placement, routing, timing closure and signoff, while partnering with hardware and system teams. You will develop flows and automation to enhance design productivity and support cutting‑edge nodes.

Qualifications

• 6+ years of experience with a Bachelor’s Degree in CS/CE or related field (or 4+ years with Master’s, or 2+ years with a Ph.D).
• 2+ years of hands‑on experience with physical design implementation flows (Synthesis, P&R, timing closure and signoff support).
• Proficiency with Synopsys or Cadence toolsets (ICC2, Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC).

Responsibilities

• Support physical design implementation, including floorplanning, placement, and routing to meet PPA goals.
• Assist timing, power, and physical signoff activities with STA-driven optimization and DRC/LVS checks.
• Develop scripts and automation to improve design productivity and flow reliability.
• Collaborate with cross‑functional teams and vendors to adapt flows for new nodes.
• Take ownership of projects and communicate analyses and results clearly.

Skills

Scripting (Python)

Scripting (TCL)

Automation

Collaboration & Communication

Debugging

Analytical skills

Cross-functional teamwork

Education

Bachelor's or higher in CS/CE or related

Master’s degree

PhD

Tools

ICC2/Fusion Compiler

Innovus

PrimeTime/Tempus

StarRC

Calibre/ICV

Job description

Samsung Austin Research and Development Center (SARC/ACL) seeks a Senior or Staff Physical Design Engineer to drive physical implementation of GPU IP, impacting power, performance and area across advanced process nodes.

You will execute floorplanning, placement, routing, timing closure and signoff, while partnering with hardware and system teams. You will develop flows and automation to enhance design productivity and support cutting‑edge nodes.