Staff Timing Engineer: GPU IP Clock Mastery & Signoff

Samsung Semiconductor; Austin (TX); On-site; USD 151,000 - 227,000; Full time

Job summary

Samsung is seeking a Staff Timing (STA) Engineer to join the GPU Physical Design team at Samsung Austin R&D Center. You will ensure timing integrity and signoff readiness for next-generation GPU IPs used in premium devices, collaborating with RTL, physical design, and EDA partners to deliver robust timing closure and power recovery.

You will work on top-level timing analysis, constraint generation, and multi-clock design across functional and test modes, with exposure to CTS, derating, UPF, and

Qualifications

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years with a Master’s, or 2+ years with a Ph.D.
• Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
• Working knowledge and experience with POCV, derating methodologies, and timing analysis.
• Strong hands-on experience with industry-standard STA tools (e.g., PrimeTime, Tempus).
• Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs.
• Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
• Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.
• Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
• Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
• Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global team environment.

Responsibilities

• Execute hands-on timing analysis at top level and generate/debug timing constraints for complex multi-clock GPU IPs across functional/test scenarios.
• Collaborate with RTL, physical design, SoC teams to identify and resolve timing issues impacting block-level and full-chip closure.
• Identify tool bugs, influence flow improvements, and explore best practices including ML-assisted exploration to improve timing quality and convergence.
• Support timing closure and signoff readiness by analyzing timing paths and applying timing budgeting, derating, and multi-voltage methodologies.
• Take initiative on moderate-to-complex projects and document analyses and results with strong ownership.

Skills

Timing analysis

Digital ASIC design

Data-driven problem solving

Communication

Collaboration

Education

Bachelor’s Degree in Computer Science/Engineering

Tools

PrimeTime

Tempus

POCV

Clock Tree Synthesis (CTS)

UPF

Derating methodologies

Scripting in Tcl/Perl/Shell/Python

Job description

Samsung is seeking a Staff Timing (STA) Engineer to join the GPU Physical Design team at Samsung Austin R&D Center. You will ensure timing integrity and signoff readiness for next-generation GPU IPs used in premium devices, collaborating with RTL, physical design, and EDA partners to deliver robust timing closure and power recovery.

You will work on top-level timing analysis, constraint generation, and multi-clock design across functional and test modes, with exposure to CTS, derating, UPF, and