Staff R&D Engineer: Advanced Packaging & SIP

Broadcom

San Jose (CA)

On-site

USD 167,000 - 268,000

Full time

14 days+
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Benefits offered by this job

Medical, dental, vision
401(K) matching
Employee Stock Purchase Program
Paid time off
Bonuses

Job summary

Broadcom in San Jose seeks a seasoned lead for advanced packaging and system-in-package technologies, guiding multi-chip assembly and technology roadmaps from research and development through new product introduction. The role requires strong collaboration with internal IC teams and external foundries, and a track record of delivering complex packaging projects.

The ideal candidate has 15+ years in semiconductor process technology and manufacturing, with a strong data-analysis background and

Qualifications

  • Broad knowledge of advanced packaging and silicon process technologies.
  • Experience with design of serial and parallel interfaces for chip-to-chip and external module communication.
  • Experience with yield data analysis and root-cause analysis tools.
  • Experience with thermal and stress simulation tools.

Responsibilities

  • Technical lead for multi-chip semiconductor assembly and system pathfinding for AI/HPC modules.
  • Owns portions of the advanced packaging roadmap and guides development from R&D to product intro.
  • Define requirements, roadmaps, evaluations, and qualification plans; provide applications support during transitions.
  • Lead technology problem solving and design/product enablement; coordinate with foundries and internal teams.
  • Act as principal investigator on new technology projects and manage multiple projects end-to-end.

Skills

Advanced packaging
System in package
Thermal solutions
Power delivery
Electrical communication
Optical communication
Chip-to-chip interfaces
Data analysis
Statistical analysis tools
problem solving

Education

MSEE in Electrical Engineering
PhD in Electrical Engineering

Tools

Statistical data analysis tools
Thermal simulation tools
Stress simulation tools

Job description

Broadcom in San Jose seeks a seasoned lead for advanced packaging and system-in-package technologies, guiding multi-chip assembly and technology roadmaps from research and development through new product introduction. The role requires strong collaboration with internal IC teams and external foundries, and a track record of delivering complex packaging projects.

The ideal candidate has 15+ years in semiconductor process technology and manufacturing, with a strong data-analysis background and

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