Staff PCIe PHY/Link Engineer - Bring-up & Debug

Samsungsemiconductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

4+ weeks paid time off

Medical/Dental/Vision benefits

401k and employee benefits

Onsite Café and gym

Job summary

Samsung Semiconductor in San Jose is seeking a dynamic engineer to develop and support cutting-edge Enterprise and Data Center SSD products, focusing on the PCIe protocol stack from PHY to Transport layers. You will work with hardware teams and vendors to bring up, train LTSSM, and validate PCIe configurations.

The role requires deep PCIe expertise, embedded C/C++, and hands-on debugging with standard tools.

Qualifications

• BS in Computer/Electrical/CS or related field with 8+ years hardware/firmware experience, or MS with 5+ years.
• Deep proficiency with the PCIe protocol spanning PHY to Transport Layer.
• Hands-on LTSSM, link training, PCIe enumeration, and flow control experience.
• Experience in C/C++ for embedded systems and debugging with UART/JTAG/ICE.

Responsibilities

• Analyze PCIe stack from PHY to Transport Layer with internal/external teams.
• Own LTSSM behavior, link training, equalization sequencing and configuration-space flows.
• Analyze and validate TLP/DLLP handling, flow control, credit management, ordering, ACK/NAK.
• Debug and optimize PHY, Link, and Transport layer issues for NVMe SSD products.
• Support PCI-SIG compliance tests and field troubleshooting at customer sites.

Skills

PCIe protocol

LTSSM & link training

C/C++ (embedded)

Firmware debugging

Logic analyzers

PCIe analyzers

UART/JTAG/ICE

Team collaboration

Education

BS in Computer/Electrical/Electronic Engineering or CS

MS in related field (5+ years)

Tools

PCIe protocol analyzers

Logic analyzers

Signal analyzers

Job description

Samsung Semiconductor in San Jose is seeking a dynamic engineer to develop and support cutting-edge Enterprise and Data Center SSD products, focusing on the PCIe protocol stack from PHY to Transport layers. You will work with hardware teams and vendors to bring up, train LTSSM, and validate PCIe configurations.

The role requires deep PCIe expertise, embedded C/C++, and hands-on debugging with standard tools.