Senior PCIe Protocol Engineer: PHY & Link Analysis

Socket.dev

San Jose (CA)

On-site

USD 163,000 - 253,000

Full time

5 days ago

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Benefits offered by this job

4+ weeks paid time off

Medical/Dental/Vision

Onsite gym/cafe

Job summary

Samsung Semiconductor in San Jose, CA seeks an engineer to develop and support PCIe host interface firmware for enterprise NVMe SSD products. You will work across PHY through Transaction/Transport layers, bringing up links and debugging LTSSM, with onsite field support and up to 25% travel.

Required: BS/MS in a relevant field and 8+ years of hardware/firmware experience, strong C/C++, and proficiency with PCIe protocol analyzers and JTAG/ICE debuggers.

Qualifications

BS in Computer/Electrical/Electronic Engineering or CS; 8+ years hardware/firmware experience or MS with 5+ years.
Deep proficiency with PCIe protocol from PHY to Transaction/Transport layers.
Strong embedded C/C++ software experience and debugging skills.

Responsibilities

Understand PCIe PHY/Link architecture and LTSSM; guide LTSSM training and enumeration.
Analyze and validate TLP/DLLP handling, flow control, and error management (AER).
Debug complex PHY/Link/Transport issues during bring‑up and NVMe SSD product life cycle.
Support industry PCIe compliance tests and provide onsite field support.

Skills

PCIe protocol

Embedded C/C++

UART/JTAG/ICE

LTSSM

PCIe protocol analyzers

Logic analyzers

Signal analyzers

Education

BS in Computer/Electrical/Electronic Eng or CS

MS with 5+ years experience

Tools

PCIe protocol analyzers

Logic analyzers

Signal analyzers

Job description

Required: BS/MS in a relevant field and 8+ years of hardware/firmware experience, strong C/C++, and proficiency with PCIe protocol analyzers and JTAG/ICE debuggers.

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