Senior SSD Hardware Engineer — PCIe & SI Lead

Micron Technology; Boise (ID); On-site; USD 164,000 - 280,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off & holidays

Bonuses and equity

Job summary

Micron Technology is seeking a highly motivated SSD Hardware Engineer to develop next-generation SSD products, focusing on hardware architecture, high-speed interfaces, SI/PI, and system-level integration. The role involves collaboration across firmware, validation, manufacturing, reliability, and customer support teams to ensure robust hardware builds and DFx-driven cost optimization.

The position requires hands-on lab experience with high-bandwidth signals (20–35 GHz), PCIe, DDR/ONFI, and a

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• 5+ years hardware build experience in SSD/storage/high-performance computing systems.

Responsibilities

• Collaborate with cross-functional teams to meet firmware, system, performance, reliability, and manufacturability requirements.
• Own SSD hardware development activities across the product lifecycle including schematic capture, simulations, and production support.
• Define PCB stack-up specifications and signal integrity/power integrity considerations.

Skills

High-speed signal integrity

PCB build & layout

Schematic capture

Measurement & test (SI lab)

PCIe familiarity

DDR memory subsystems

Power integrity

SPICE or analog modeling

Automation/testing frameworks

Team mentorship

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

SPICE

PCIe compliance equipment

Schematic capture tools

PCB layout tools

Job description

Micron Technology is seeking a highly motivated SSD Hardware Engineer to develop next-generation SSD products, focusing on hardware architecture, high-speed interfaces, SI/PI, and system-level integration. The role involves collaboration across firmware, validation, manufacturing, reliability, and customer support teams to ensure robust hardware builds and DFx-driven cost optimization.

The position requires hands-on lab experience with high-bandwidth signals (20–35 GHz), PCIe, DDR/ONFI, and a