Staff Engineer, PCIe: PHY & Link Mastery

Conductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

4+ weeks paid time off

Fertility/adoption support

Onsite café & gym

Flexible work environment

Job summary

Samsung Semiconductor in San Jose, CA is seeking a seasoned hardware/firmware engineer to advance PCIe-based SSD products. You will own protocol stack bring-up, LTSSM behaviour, and cross-layer debugging across PHY, Data Link, and Transaction layers.

The role requires strong C/C++ embedded skills, experience with PCIe analyzers, and collaboration with hardware teams. Extensive travel (up to 25%) is expected to support field and lab activities.

Qualifications

• BS or MS in Engineering or CS with 8+ years of hardware/firmware experience
• Deep proficiency with PCIe across PHY/Lane/Transaction layers
• Hands-on LTSSM, link training, and PCIe enumeration expertise
• Experience debugging LV/UX issues with embedded firmware and C/C++

Responsibilities

• Analyze PCIe protocol stack from PHY to Transaction layer
• Own LTSSM behavior, training, and enumeration during bring-up
• Analyze and validate TLP/DLLP handling, flow control, and AER
• Debug complex PHY/Link/Transport issues across NVMe/SSD products
• Support industry PHY/Link compliance tests and field tasks
• Travel up to 25% to customer sites and labs

Skills

PCIe protocol stack

LTSSM

C/C++ (embedded)

UART/JTAG/ICE debugging

PCIe protocol analyzers

Logic/Signal analyzers

Firmware debugging

Cross-functional collaboration

Education

BS in Computer/Electrical/Electronic Engineering or Computer Science

MS in Computer/Electrical/Electronic Engineering or Computer Science

Tools

PCIe protocol analyzers

Logic analyzers

Signal analyzers

UART/JTAG/ICE debuggers

Job description

Samsung Semiconductor in San Jose, CA is seeking a seasoned hardware/firmware engineer to advance PCIe-based SSD products. You will own protocol stack bring-up, LTSSM behaviour, and cross-layer debugging across PHY, Data Link, and Transaction layers.

The role requires strong C/C++ embedded skills, experience with PCIe analyzers, and collaboration with hardware teams. Extensive travel (up to 25%) is expected to support field and lab activities.