Staff Package Design Engineer - Power & Chiplet Packages

Renesas; Town of Texas (WI); On-site; USD 120,000 - 180,000; Full time

Job summary

Renesas is seeking a Staff Package Design Engineer to join our Advanced Silicon Packaging team in the US (Austin, TX or Tempe, AZ). You will design and deliver high-performance semiconductor packages, including power modules, FCBGA, SiP, WLCSP, and multi-die architectures.

You will collaborate with silicon design, SI/PI, thermal, reliability, and manufacturing teams to optimize package layouts, ensure DRC/LVS compliance, and support production release through Gerber data and documentation.

Qualifications

• 4+ years in package CAD layout, substrate design, or advanced package development; 6+ years preferred.
• Strong background in power module packaging, FCBGA, SiP, WLCSP, and multi-die architectures.
• Proficient with Cadence Allegro, Xpedition, or equivalent CAD platforms.
• Experience applying OSAT/DFM/ DFA rules and manufacturing release standards.
• Experience interfacing with Tier-1 OSATs, suppliers, foundries, and cross-functional teams.
• Understanding of SI/PI fundamentals, high-speed routing, impedance control, and crosstalk mitigation.
• Excellent communication, presentation, and documentation skills in global teams.

Responsibilities

• Execute package layout design and development for advanced packages.
• Develop and maintain package CAD databases for manufacturability and reliability.
• Manage design cycle including schematic, netlist, footprints, layout, verification, and release outputs.
• Create substrate and RDL layouts, bump maps, escape routing, and power/ground features.
• Collaborate with SI/PI, thermal, reliability, and manufacturing teams for co-optimization.
• Ensure designs comply with foundry, OSAT, and vendor design rules.
• Support ECO cycles, revisions, and release documentation.

Skills

Package CAD layout

Substrate design

Advanced packaging

High-speed routing

Impedance control

Power/ground distribution

Cross-functional collaboration

Documentation skills

Education

Bachelor's or Master's in Electrical Engineering or related

Tools

Cadence Allegro Package Designer / SiP Layout

Siemens Xpedition Substrate Integrator

Job description

Renesas is seeking a Staff Package Design Engineer to join our Advanced Silicon Packaging team in the US (Austin, TX or Tempe, AZ). You will design and deliver high-performance semiconductor packages, including power modules, FCBGA, SiP, WLCSP, and multi-die architectures.

You will collaborate with silicon design, SI/PI, thermal, reliability, and manufacturing teams to optimize package layouts, ensure DRC/LVS compliance, and support production release through Gerber data and documentation.