Staff DV Engineer - High-Perf CPU Cores (Equity)

Socket.dev; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Healthcare

Retirement plan

Paid time off

Job summary

SiFive, a leader in RISC‑V compute, seeks a Staff Design Verification Engineer to drive verification of high-performance CPU core units. This Staff role within the CPU Design Verification organization focuses on Frontend, Midcore, Load-Store Unit, and hardware prefetch areas, with a bias toward strategy and early risk identification.

You will collaborate with architecture, RTL, performance and verification teams to ensure design intent is captured, risks identified early, and signoff quality is

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related field.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
• Experience in Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Knowledge of verification flow methodology: test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, closure.
• Strong debug skills and ability to translate architectural intent into verification strategy and execution.

Responsibilities

• Own verification planning and execution for one or more high-performance out-of-order CPU core areas across Frontend, Midcore, Load-Store Unit, or related core-level interactions.
• Drive block-level and core-level verification planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural behavior.
• Define verification strategies for challenging behaviors such as instruction fetch, branch prediction, issue/dispatch, pipeline interactions, memory ordering, and hardware prefetch correctness.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models exposing corner cases.
• Partner with architecture and design teams from early feature-definition stages to review specifications and improve verification quality.
• Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
• Contribute reusable methodology and infrastructure to improve productivity across future core generations.

Skills

SystemVerilog

UVM

CPU/core verification

ASIC/SoC verification

Debugging

Computer architecture

Constrained-random / directed stimulus

Python

C/C++

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Python

C/C++

Job description

SiFive, a leader in RISC‑V compute, seeks a Staff Design Verification Engineer to drive verification of high-performance CPU core units. This Staff role within the CPU Design Verification organization focuses on Frontend, Midcore, Load-Store Unit, and hardware prefetch areas, with a bias toward strategy and early risk identification.

You will collaborate with architecture, RTL, performance and verification teams to ensure design intent is captured, risks identified early, and signoff quality is