Staff Digital Design Engineer: Low-Power SoC & Clocking

Silicon Labs; Austin (TX); On-site; USD 143,150 - 265,850; Full time

Benefits offered by this job

Great medical, dental, and vision plans

401k plan with match

Flexible PTO schedule

Monthly wellness offerings

Free snacks

Job summary

Silicon Labs in Austin, TX, is looking for a Staff Digital Design Engineer to develop advanced SoC devices for the wireless IoT market. This role entails designing low-power architectures, collaborating on power management strategies, and overseeing the integration of complex digital subsystems.

The position requires strong RTL design expertise and 10-20 years of experience in digital CMOS IC design. In addition to a competitive salary, benefits include medical plans, 401k matching, and flexible PTO.

Qualifications

• Experience in digital CMOS IC design for 10-20 years.
• Ability to lead teams and design digital subsystems.
• Demonstrated knowledge of integration of complex subsystems.

Responsibilities

• Develop SoC architectures for IoT wireless market.
• Collaborate with architects on power management strategies.
• Design and integrate clocking infrastructure.

Skills

RTL design expertise using Verilog/System Verilog

SoC clocking architectures

low-power design methodologies

on-chip bus protocols

Python, Perl, Tcl scripting

communication skills

Education

BS/MS in Electrical Engineering

Tools

logic simulators

power analysis tools

revision control systems (Perforce, Git)

Job description

Silicon Labs in Austin, TX, is looking for a Staff Digital Design Engineer to develop advanced SoC devices for the wireless IoT market. This role entails designing low-power architectures, collaborating on power management strategies, and overseeing the integration of complex digital subsystems.

The position requires strong RTL design expertise and 10-20 years of experience in digital CMOS IC design. In addition to a competitive salary, benefits include medical plans, 401k matching, and flexible PTO.