Senior Wireless SoC Architect & Technical Lead

Silicon Laboratories Inc.; Austin (TX); On-site; USD 161,000 - 298,000; Full time

Benefits offered by this job

Great medical benefits

Competitive salary

401k with match

Equity rewards

Job summary

Silicon Labs in Austin, TX seeks a Chip Lead to own the architecture, design, integration, and tapeout of wireless SoCs, driving technical decisions to meet performance, power, and cost targets.

You will lead cross-functional teams across verification, physical design, and validation, ensure schedule and milestones, and coordinate silicon bring-up to production readiness. The role requires deep expertise in low-power design, IP integration, and validation across multiple regions.

Qualifications

• Bachelor or Master’s degree in Electrical or Computer Engineering.
• 12+ years of experience in SoC or IP development.
• Proven ability to lead complex chip development projects across cross-functional teams.

Responsibilities

• Lead the development and execution of wireless SoCs from definition through bring-up and production.
• Define and plan SoC architecture with stakeholders across marketing, systems, and IP teams.
• Provide input on architectural decisions, tradeoffs, and feasibility; drive design signoff processes.
• Coordinate verification, physical design, and validation to ensure silicon readiness.
• Drive risk identification and issue resolution across multiple geographies and teams.

Skills

SoC architecture

Cross-functional leadership

Low-power design

Design verification

Scripting (Python, Perl, Tcl)

Verilog/SystemVerilog

ARM/RISC-V/processor knowledge

Education

Electrical or Computer Engineering degree

Tools

Verilog

SystemVerilog

Perl

Python

Tcl

Shell scripting

Job description

Silicon Labs in Austin, TX seeks a Chip Lead to own the architecture, design, integration, and tapeout of wireless SoCs, driving technical decisions to meet performance, power, and cost targets.

You will lead cross-functional teams across verification, physical design, and validation, ensure schedule and milestones, and coordinate silicon bring-up to production readiness. The role requires deep expertise in low-power design, IP integration, and validation across multiple regions.