Senior Digital SoC Designer - Wireless & Low-Power

Top Workforce Solutions, LLC; Chandler (AZ); Sur place; USD 123 000 - 168 000; Plein temps

Avantages offerts par ce poste

Performance-based bonuses

Excellent benefits package

Up to 25% travel

Résumé du poste

Top Workforce Solutions, LLC is seeking a Senior Digital SoC Design Engineer to contribute to next-generation wireless semiconductor solutions. The role centers on digital SoC design, RTL development, and ASIC implementation in a collaborative, cross-functional setting.

The ideal candidate has extensive experience in RTL design, Verilog/SystemVerilog, and low-power ASIC flows, with strong problem-solving skills and international teamwork experience.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or a related technical field.
• Minimum 12 years of experience in digital SoC/ASIC design with emphasis on low-power applications.
• Proficiency in RTL design using Verilog/SystemVerilog, synthesis, SDC timing constraints, and timing analysis.
• Experience with ASIC design methodologies including LINT, formal verification, CDC/RDC, MBIST/DFT, and power estimation.
• Strong understanding of ARM/MIPS architectures, AMBA/AXI bus protocols, and interfaces such as USB, Ethernet, I2C, and SPI.

Responsabilités

• Design and develop digital SoC solutions from architecture to tape-out.
• RTL development with Verilog/SystemVerilog, synthesis, timing analysis, and optimization.
• Execute ASIC design flows to meet functional, performance, power, and qualification requirements.
• Collaborate with verification, physical design, and cross-functional teams across disciplines.
• Support silicon validation, debugging, and product qualification activities.
• Develop and optimize low-power design techniques and power estimation methodologies.
• Participate in design reviews to ensure conformance to specs.
• Coordinate with external IP providers and global teams to resolve challenges.
• Support integration and implementation across multiple engineering domains.

Connaissances

RTL design

Verilog/SystemVerilog

SDC timing constraints

Timing analysis

LINT/formal verification

CDC/RDC

MBIST/DFT

Power estimation

ARM/MIPS architectures

AMBA/AXI bus

USB/Ethernet/I2C/SPI

Scripting: TCL/Perl/Python

Bus matrix architecture

Cross-functional collaboration

Formation

Bachelor's degree in Electrical/Computer Engineering

Master's degree (preferred)

Outils

UVM/OVM verification

FPGA prototyping

Board-level debugging

Silicon validation

Description du poste

Top Workforce Solutions, LLC is seeking a Senior Digital SoC Design Engineer to contribute to next-generation wireless semiconductor solutions. The role centers on digital SoC design, RTL development, and ASIC implementation in a collaborative, cross-functional setting.

The ideal candidate has extensive experience in RTL design, Verilog/SystemVerilog, and low-power ASIC flows, with strong problem-solving skills and international teamwork experience.