Staff Digital Design Engineer – SOC Low Power, Clocking & Integration

Silicon Laboratories Inc.; Austin (TX); On-site; USD 143,150 - 265,850; Full time

Benefits offered by this job

401(k) plan with match

Equity rewards (RSUs)

Flexible PTO schedule

Tuition reimbursement

Onsite gym

Job summary

Silicon Laboratories Inc. is seeking a Staff Digital Design Engineer in Austin, TX, to develop state-of-the-art, low-power SoC devices for the IoT market. The role involves leading design teams and collaborating on complex chip architectures aimed at optimizing performance and power efficiency.

Applicants should possess a strong background in digital design with over 10 years of experience, particularly in low-power methodologies and SoC integration. Benefits include competitive salary, medical plans, 401(k) matching, work-life balance, and more.

Qualifications

• 10-20 years of professional experience in digital CMOS IC design.
• Strong experience with industry-standard on-chip bus protocols.
• Experience integrating complex subsystems into large SoCs.

Responsibilities

• Develop complex SOC/chip architectures for low-power applications.
• Define and implement SoC-level low-power architecture.
• Collaborate to define power-management strategies.

Skills

RTL design expertise using Verilog/System Verilog

Low-power design methodologies

Team leadership

Knowledge of embedded processor systems

Experience with scripting and automation

Education

BS/MS in Electrical Engineering

Tools

Python

Perforce

Git

Job description

Staff Digital Design Engineer – SOC Low Power, Clocking & Integration (Austin, TX)

Responsibilities

The Role as a Staff Digital Design Engineer, you will develop world‑class, highly integrated, low‑power, System‑on‑Chip device to serve the IoT wireless market.

• Develop complex SOC/chip architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios
• Define and implement SoC‑level low‑power architecture, including power domains, retention, isolation, level shifters, and power sequencing
• Develop and integrate UPF/CPF‑based power intent across subsystem and SoC hierarchies
• Collaborate with architects to define power‑management strategies that meet performance, power, and area targets
• Design and integrate clocking infrastructure, including clock generation, clock distribution, clock gating, clock muxing, reset architectures, and clock monitoring mechanisms
• Drive RTL design and integration of power‑management controllers, clock controllers, reset controllers, and related infrastructure IPs
• Prepare and hold architecture, design, and verification reviews with technical staff throughout project lifecycle
• Analyze and debug low‑power and clocking issues identified during simulation, emulation, synthesis, and silicon bring‑up
• Architect and integrate SoC interconnects and bus fabrics, including AXI, AHB, APB, and other on‑chip communication protocols
• Lead small teams of design engineers to architect, design and verify digital subsystems
• Drive subsystem and SoC integration activities, ensuring seamless connectivity between processors, memories, peripherals, accelerators, and third‑party IPs
• Drive RTL development and integration of infrastructure IPs, including clock controllers, reset controllers, power‑management controllers, DMA engines, and bus fabric components
• Analyze and debug integration, clocking, power, CDC/RDC, and protocol‑related issues throughout the development cycle
• Validate/bring‑up designs on silicon, providing support to cross‑functional teams

Qualifications

BS/MS in Electrical Engineering and 10‑20 years of professional experience in digital CMOS IC design

• Demonstrated ability to lead small teams designing complex digital subsystems
• Strong RTL design expertise using Verilog/System Verilog
• Solid understanding of SoC clocking architectures, clock domain crossing (CDC), reset domain crossing (RDC), synchronization techniques, and timing considerations
• Extensive experience with low‑power design methodologies, including UPF, power gating, retention, isolation, level shifting, and power‑aware verification
• Strong experience with industry‑standard on‑chip bus protocols such as AXI, AHB, APB, and related interconnect architectures
• Experience integrating complex subsystems, processor clusters, memory subsystems, and third‑party IPs into large SoCs
• Knowledge of embedded processor systems and C coding
• Experience with logic simulators for both RTL and gate‑level simulation, design/waveform browsers, and power analysis tools
• Experience with logic synthesis and timing constraints
• Experience working with backend team to optimize design for power, performance, and area
• Experience working with analog and mixed signal designs, to support design integration and verification of these subsystems in SOC
• Experience with scripting and automation; knowledge of Python, Perl, and Tcl
• Experience with revision control and configuration management systems (such as Perforce, Git, Methodics)
• Excellent written and verbal communication skills
• Demonstrated ability to generate high output in a self‑driven manner
• Experience with artificial intelligence (AI)‑powered tools and technologies used to enhance productivity, analysis, and decision‑making

Benefits

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
• Highly competitive salary
• 401(k) plan with match and Roth plan option
• Equity rewards (RSUs)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• Back‑up childcare
• Commuter benefits, legal benefits, pet insurance
• Flexible PTO schedule
• 3 paid volunteer days per year
• Charitable contribution match
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO

The annualized base pay range for this role is expected to be between $143,150 and $265,850 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed, and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.

Silicon Labs is an equal‑opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job‑related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.