Staff DFT Engineer – HBM Memory Test Architect

Micron; Richardson (TX); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, a world leader in memory and storage solutions, seeks a Staff DFT Design Engineer to define and implement DFT architectures for HBM products in Richardson, TX. You will collaborate across multiple engineering teams to deliver robust fault-tolerant designs.

Responsibilities include designing DFT structures, testing interaction across wafer to SiP, and supporting yield analysis and debug. A strong background in digital design and DFT is essential, with experience in RTL and

Qualifications

• Bachelor’s or Master’s in EE/CE or related field.
• Strong fundamentals in digital design and DFT concepts (scan, MBIST, boundary scan, JTAG).
• Experience with RTL design (SystemVerilog/VHDL) and logic integration.

Responsibilities

• Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at-speed test structures.
• Develop DFT solutions for base die and DRAM die in stacked-die configurations.
• Design and integrate test access mechanisms for wafer probe, cube test, and SiP/system test flows.
• Collaborate with Product Engineering and Test Enablement to align DFT with manufacturing test costs.
• Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon.
• Work with logic, analog, layout, verification, and physical design teams to ensure correct DFT implementation.

Skills

Digital design fundamentals

DFT concepts (scan, MBIST, boundary)

RTL design (SystemVerilog/VHDL)

JTAG/test access

Semiconductor test flows

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Job description

Micron Technology, a world leader in memory and storage solutions, seeks a Staff DFT Design Engineer to define and implement DFT architectures for HBM products in Richardson, TX. You will collaborate across multiple engineering teams to deliver robust fault-tolerant designs.

Responsibilities include designing DFT structures, testing interaction across wafer to SiP, and supporting yield analysis and debug. A strong background in digital design and DFT is essential, with experience in RTL and