Staff Design Engineer: GPU/TPU Compute Engines (Equity)

Oxmiq Labs; Campbell (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity participation

Medical, dental, and vision coverage

Job summary

OXMIQ Labs in the Bay Area is seeking a Staff Design Engineer to join our GPU/AI accelerator development team. You will shape architecture, RTL design, integration, and verification of high-performance compute engines.

The ideal candidate has 5–10 years of ASIC/SoC experience, strong SystemVerilog skills, and a track record of delivering complex blocks from microarchitecture to tapeout. This on-site role offers collaboration with architecture, verification, PD, firmware, and software teams.

Qualifications

• 5–10 years of ASIC/SoC design or related semiconductor development.
• Proficient in SystemVerilog/Verilog RTL design.
• Experience with tensor/matrix processing.
• Strong digital design fundamentals and computer architecture.
• Experience with industry-standard EDA tools and RTL simulation/debug.
• Ability to own a complex design block end-to-end.

Responsibilities

• Define and implement microarchitecture for GPU/TPU compute engines and accelerator blocks
• Develop high-quality, synthesizable SystemVerilog/RTL
• Analyze performance, area, power, and timing tradeoffs and drive design optimization
• Develop block-level and system-level verification strategies and debug complex hardware issues
• Collaborate closely with architecture, verification, physical design, firmware, and software teams
• Participate in design reviews and drive technical decisions across multiple engineering teams
• Contribute to pre-silicon performance modeling, benchmarking, and post-silicon debug

Skills

SystemVerilog RTL

RTL design

Computer architecture

Performance optimization

EDA tools

SystemVerilog

Education

BS/MS/PhD in Computer Engineering, Electrical Engineering

Tools

RTL simulation tools

FPGA prototyping

Job description

OXMIQ Labs in the Bay Area is seeking a Staff Design Engineer to join our GPU/AI accelerator development team. You will shape architecture, RTL design, integration, and verification of high-performance compute engines.

The ideal candidate has 5–10 years of ASIC/SoC experience, strong SystemVerilog skills, and a track record of delivering complex blocks from microarchitecture to tapeout. This on-site role offers collaboration with architecture, verification, PD, firmware, and software teams.