Staff Design Engineer – TPU/GPU Design

Oxmiq Labs; Campbell (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity participation

Medical, dental, and vision coverage

Job summary

OXMIQ Labs in the Bay Area is seeking a Staff Design Engineer to join our GPU/AI accelerator development team. You will shape architecture, RTL design, integration, and verification of high-performance compute engines.

The ideal candidate has 5–10 years of ASIC/SoC experience, strong SystemVerilog skills, and a track record of delivering complex blocks from microarchitecture to tapeout. This on-site role offers collaboration with architecture, verification, PD, firmware, and software teams.

Qualifications

• 5–10 years of ASIC/SoC design or related semiconductor development.
• Proficient in SystemVerilog/Verilog RTL design.
• Experience with tensor/matrix processing.
• Strong digital design fundamentals and computer architecture.
• Experience with industry-standard EDA tools and RTL simulation/debug.
• Ability to own a complex design block end-to-end.

Responsibilities

• Define and implement microarchitecture for GPU/TPU compute engines and accelerator blocks
• Develop high-quality, synthesizable SystemVerilog/RTL
• Analyze performance, area, power, and timing tradeoffs and drive design optimization
• Develop block-level and system-level verification strategies and debug complex hardware issues
• Collaborate closely with architecture, verification, physical design, firmware, and software teams
• Participate in design reviews and drive technical decisions across multiple engineering teams
• Contribute to pre-silicon performance modeling, benchmarking, and post-silicon debug

Skills

SystemVerilog RTL

RTL design

Computer architecture

Performance optimization

EDA tools

SystemVerilog

Education

BS/MS/PhD in Computer Engineering, Electrical Engineering

Tools

RTL simulation tools

FPGA prototyping

Job description

OXMIQ designs GPU and AI silicon for large-scale model inference and training, and is building the system software and analysis platforms that prove out those designs before they reach customers. We are a startup driving innovation across the full stack — from atoms to agents — and we move fast on the strength of our own tools.

About the Role

We are looking for a Staff Design Engineer to join our GPU/AI accelerator development team. You will play a key role in the architecture, RTL design, integration, and verification of high-performance TPU/GPU compute engines.

The ideal candidate has strong experience designing complex hardware blocks for GPUs, TPUs, AI accelerators, or other high-performance processors, with a deep understanding of processor pipelines, parallel computing, memory systems, and SoC interconnects.

Responsibilities

• Define and implement microarchitecture for GPU/TPU compute engines and accelerator blocks
• Develop high-quality, synthesizable SystemVerilog/RTL
• Analyze performance, area, power, and timing tradeoffs and drive design optimization
• Develop block-level and system-level verification strategies and debug complex hardware issues
• Collaborate closely with architecture, verification, physical design, firmware, and software teams
• Participate in design reviews and drive technical decisions across multiple engineering teams
• Contribute to pre-silicon performance modeling, benchmarking, and post-silicon debug

Basic Qualifications

• 5–10 years of experience in ASIC/SoC design or related semiconductor development
• Strong experience with SystemVerilog/Verilog RTL design
• Experience with one or more of:
• Tensor/matrix processing
• Strong understanding of digital design fundamentals, computer architecture, and performance optimization
• Experience with industry-standard EDA tools and RTL simulation/debug
• Ability to independently own a complex design block from microarchitecture through RTL, verification, and tapeout

Preferred Qualifications

• Experience with NVIDIA/AMD/Google TPU or similar GPU/AI accelerator architectures
• Experience with performance modeling and workload-driven architecture optimization
• Familiarity with CUDA, PTX, MLIR, PyTorch, or other AI software stacks
• Experience with formal verification, emulation, FPGA prototyping, or advanced simulation environments
• Experience working on complex SoCs from architecture through silicon

Education

BS/MS/PhD in Computer Engineering, Electrical Engineering, or a related field — or equivalent practical experience.

This is a hands-on, individual-contributor role based on-site at OXMIQ's Bay Area headquarters, working closely with architecture, verification, physical design, firmware, and software teams to take compute engine designs from microarchitecture through tapeout. This role requires eligibility to work in the United States. AI-assisted development tools (Claude Code or equivalent) are a standard part of engineering practice at OXMIQ and are expected in daily work.

OXMIQ offers a competitive compensation package, including base salary, equity participation, comprehensive medical, dental, and vision coverage, and the opportunity to contribute to foundational silicon and software technology.

OXMIQ is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected characteristic.