RTL Design Engineer, TPU Compute

Google Inc.; Austin (TX); Hybrid; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is shaping the future of AI/ML hardware acceleration by developing TPU technology and custom silicon solutions. You will contribute design and verification expertise focused on TPU architecture within AI/ML systems, collaborating across software, architecture, and cross-functional teams.

The role emphasizes driving innovation in cutting-edge hardware, with opportunities to influence compute subsystems and integration in hyperscale environments, while engaging with teams worldwide.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent practical experience).
• 4 years of experience with digital design using SystemVerilog RTL.
• Experience with Computer Architecture.

Responsibilities

• Develop SystemVerilog RTL to implement ASIC logic per guidelines.
• Work with DV teams to create testplans and verify RTL.
• Collaborate with physical design to ensure timing closure and physical requirements.
• Review compute subsystem design microarchitecture specifications.

Skills

SystemVerilog RTL

Digital design

Computer Architecture

Mentoring

Education

Bachelor's degree (EE/CE/CS) or equivalent

Job description

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

X Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Austin, TX, USA.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital design experience using SystemVerilog RTL.
• Experience with Computer Architecture.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience interacting with software, architecture, and other cross-functional teams.
• Experience applying computer architecture principles to solve open-ended problems.
• Knowledge of processor design, accelerators, or memory hierarchies.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Work on their own to create and review Compute subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with design validation (DV) teams to create testplans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.