Staff ASIC/SoC RTL & Microarchitecture Engineer — Edge AI

Certified Employment Group; Santa Clara (CA); On-site; USD 195,000 - 226,000; Full time

Job summary

Certified Employment Group is seeking a Staff ASIC/SoC Design Engineer – RTL & Microarchitecture in Santa Clara, CA. The role requires deep RTL/SoC expertise and hands-on design across video/image processing, AI accelerators, and microarchitectures.

You will influence RTL optimization, collaborate on chip bring-up, and contribute to silicon-ready IPs and subsystems for edge AI applications. Onsite role with strong compensation and RSU opportunities.

Qualifications

• Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, with 5–10 years of experience.
• Good understanding of computer architecture, logic design, and VLSI design.
• Hands‑on experience designing and implementing complex ASIC/SoC IPs or subsystems using RTL.
• Experience with AI accelerators, vector processors, RISC‑V CPUs, image processing pipelines, HEVC/AV1 codecs, or LPDDR5/LPDDR6.
• Knowledge of SystemVerilog, Verilog, Python, and Perl.
• Knowledge of design verification and functional coverage.
• Ability to program in scripting languages and write assembly-language programs.
• Strong communication, collaboration, and problem-solving skills.

Responsibilities

• Design and implement video compression, image processing, vector computation, and flexible compute systems for future AI agents and LLM inference.
• Work with processor cores and memory subsystems using SystemVerilog.
• Design and implement complex ASIC/SoC IPs and subsystems, owning RTL development and contributing to microarchitecture decisions.
• Perform logic design, implementation, and verification using Verilog, SystemVerilog, and scripting languages.
• Synthesize and optimize RTL for timing, area, and power.
• Explore microarchitecture tradeoffs through rapid modeling with Python/Perl.
• Develop front-end methodologies and tool flows.
• Participate in chip bring-up and testing.
• Analyze code coverage and functional coverage and advise verification team.

Skills

RTL design

SystemVerilog

Verilog

Python

Perl

Education

Master’s degree in Electrical Engineering/EE/CE

Tools

SystemVerilog

Verilog

Python

Perl

Job description

Certified Employment Group is seeking a Staff ASIC/SoC Design Engineer – RTL & Microarchitecture in Santa Clara, CA. The role requires deep RTL/SoC expertise and hands-on design across video/image processing, AI accelerators, and microarchitectures.

You will influence RTL optimization, collaborate on chip bring-up, and contribute to silicon-ready IPs and subsystems for edge AI applications. Onsite role with strong compensation and RSU opportunities.