Application Specific Integrated Circuit Design Engineer

The Richmond Group USA; San Jose (CA); On-site; USD 171,000 - 209,000; Full time

Benefits offered by this job

Stock options

Annual bonus

Work-life balance

Job summary

The Richmond Group USA partnering with a leading semiconductor company seeks an ASIC Design Engineer RTL and SoC for its San Jose R&D team. This hands-on role covers video and image-processing ICs across microarchitecture, RTL design, SoC integration, verification, tape-out, and chip bring-up.

You will join a stable, long-tenured engineering group with ownership across the full chip-development lifecycle, in a Bay Area market that values long-term viability.

Qualifications

• Bachelor’s degree in Electrical Engineering or EECS; master’s preferred.
• Minimum three years in VLSI/ASIC/RTL or digital IC design.
• Experience with Verilog or SystemVerilog and complex-block microarchitecture.
• Familiarity with verification planning, coverage, and multi-clock-domain designs.
• Knowledge of image processing or signal processing.
• Exposure to scripting, synthesis, static timing analysis, DFT, or ATPG.
• Strong execution, attention to detail, and ability to work independently and collaboratively.

Responsibilities

• Develop complex ASICs for video-surveillance and automotive applications.
• Own microarchitecture definition, RTL design, integration, and verification.
• Develop test plans and support block-level and whole-chip validation.
• Work with multi-clock-domain designs, synthesis, timing closure, DFT, and ATPG.
• Collaborate with test, production, firmware, and other engineering teams.
• Contribute across the complete chip-development lifecycle.

Skills

VLSI/ASIC/digital IC design

Verilog/SystemVerilog

Multi-clock-domain design

Verification planning/coverage

Image processing/Signal processing

Scripting (Python)

DFT/ATPG

Education

Bachelor’s degree in Electrical Engineering/EECS

Master’s degree preferred

Tools

Synthesis

Static timing analysis

DFT/ATPG tools

Scripting languages (Python, Tcl)

Job description

The Richmond Group USA is partnering with an established semiconductor company to identify a ASIC Design Engineer RTL and SoC for its San Jose R&D team.

This is a hands-on role supporting complex video and image-processing ICs across microarchitecture, RTL design, SoC integration, verification, tape-out, and chip bring-up. You will join a stable, long-tenured engineering team where designers can take meaningful ownership across the complete chip-development lifecycle and build for the long term. That level of stability is especially meaningful in today’s Bay Area semiconductor market.

What You’ll Be Doing

• Develop complex ASICs for video-surveillance and automotive applications
• Own microarchitecture definition, RTL design, integration, and verification activities
• Develop test plans and support block-level and whole-chip validation
• Work with multi-clock-domain designs, synthesis, timing closure, DFT, and ATPG
• Collaborate with test, production, firmware, and other engineering teams
• Contribute across the complete chip-development lifecycle

What We’re Looking For

• Bachelor’s degree in Electrical Engineering, EECS, or a related discipline; master’s degree preferred
• At least three years of VLSI, ASIC, RTL, or digital IC design experience, with deeper experience strongly valued
• Experience with Verilog or SystemVerilog and complex-block microarchitecture
• Familiarity with verification planning, coverage, and multi-clock-domain designs
• Knowledge of image processing or signal processing
• Exposure to scripting, synthesis, static timing analysis, DFT, or ATPG
• Strong execution, attention to detail, and the ability to work independently and collaboratively

Candidates do not need to meet every preferred qualification. The company is open to engineers whose overall ASIC and SoC development experience demonstrates strong technical depth.

What’s in It for You

• Base salary up to $190,000
• Annual salary increases historically averaging 4% to 6%
• Stock options included as part of the compensation package
• Eligible for an annual performance bonus
• Stable, collaborative environment with strong work-life balance
• Broad ownership across the full chip-development lifecycle
• High-visibility role within a lean R&D team
• Opportunity to collaborate with international engineering teams

This position is fully onsite in San Jose, California. Candidates must be authorized to work in the United States without current or future sponsorship.

All inquiries will be kept confidential, and candidate information will not be shared with the hiring organization without prior approval.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, gender identity, sexual orientation, national origin, age, disability, genetic information, military or veteran status, or any other characteristic protected by applicable law.