Staff ASICSoC Design Engineer

Certified Employment Group; Santa Clara (CA); On-site; USD 195,000 - 226,000; Full time

Job summary

Certified Employment Group in Santa Clara, CA is seeking a Staff ASIC/SoC Design Engineer with 5–10 years of VLSI/ASIC experience. This full-time role focuses on video compression, image processing, and edge AI applications, offering ownership of chip aspects from architecture to silicon.

You will work with SystemVerilog/Verilog, Python, and Perl across RTL design, verification, and microarchitecture exploration, collaborating with cross-functional teams to drive timing, power, and area

Qualifications

• Master’s degree required in Electrical/Electronics/Computer Engineering; 5–10 years of experience.
• Strong understanding of computer architecture, logic design, and VLSI design.
• Proficiency with SystemVerilog/Verilog; Python and Perl scripting.
• Experience in design verification and functional coverage preferred.

Responsibilities

• Design and implement video compression, image processing, vector computation, and flexible compute systems for AI/inference.
• Work with processor cores and memory subsystems using SystemVerilog and Verilog.
• Perform RTL synthesis, timing, area, and power optimization.
• Explore microarchitecture tradeoffs via rapid modeling with Python/Perl.
• Develop front-end methodologies and tool flows and participate in chip bring-up.

Skills

Video compression

Image processing

Vector computation

Processor cores

Memory subsystems

RTL optimization

SystemVerilog

Verilog

Python

Perl

Education

Master’s degree in Electrical Engineering/Electronics Engineering/Computer Engineering

Tools

SystemVerilog

Verilog

Python

Perl

Job description

Job Description

Job Description

Staff ASIC/SoC Design Engineer

Location: Santa Clara, CA | Candidates must currently reside in California
Schedule: Full-Time M-F, 4 days onsite
Compensation: $195,000 - $226,000 base salary. Base salary is determined based on location, experience, and the pay of employees in similar positions. Compensation package also includes new-hire RSU grants, the opportunity for annual RSU grants, and highly competitive benefits.

About the Company

Our client is a leading fabless semiconductor company at the forefront of edge AI-based computer vision. Their SoCs (Systems-on-Chips) power applications ranging from autonomous driving and ADAS to intelligent video security and robotics.

They are building the next generation of Edge AI, operating at the intersection of high-performance hardware and real-world software deployment.

The Opportunity

This is an ideal opportunity for an experienced VLSI/ASIC designer who wants broad technical exposure and meaningful ownership of the chip being built.

Rather than focusing on a narrow block or isolated function, this position provides exposure across video compression, image processing, vector computation, processor cores, memory subsystems, and flexible compute architectures for next-generation edge AI applications.

You will have the opportunity to influence microarchitecture, optimize RTL for performance, power, and area, participate in chip bring-up, and see your work progress from concept through silicon.

Responsibilities

• Design and implement video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference.
• Work with processor cores and memory subsystems using SystemVerilog, with a focus on next-generation edge AI applications including automation, robotics, and intelligent low‑power embedded systems.
• Perform logic design, implementation, and verification using Verilog, SystemVerilog, and required programming and scripting languages.
• Synthesize and optimize RTL for timing, area, and power.
• Explore microarchitecture and architectural tradeoffs through rapid modeling using scripting languages such as Python and Perl.
• Develop front-end methodologies and tool flows.
• Participate in chip bring-up and testing.
• Analyze code coverage and functional coverage and provide recommendations to the verification team to address coverage gaps.

Requirements

• Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, with 5-10 years of experience.
• Good understanding of computer architecture, logic design, and VLSI design.
• Knowledge of SystemVerilog, Verilog, Python, and Perl.
• Knowledge of design verification and functional coverage.
• Ability to program in scripting languages and write assembly-language programs.
• Strong communication, collaboration, and problem‑solving skills.
• Knowledge of logic synthesis and timing closure is preferred.