Staff ASIC/SoC Design Engineer — Edge AI & Vision

Certified Employment Group; Santa Clara (CA); On-site; USD 195,000 - 226,000; Full time

Job summary

Certified Employment Group in Santa Clara, CA is seeking a Staff ASIC/SoC Design Engineer with 5–10 years of VLSI/ASIC experience. This full-time role focuses on video compression, image processing, and edge AI applications, offering ownership of chip aspects from architecture to silicon.

You will work with SystemVerilog/Verilog, Python, and Perl across RTL design, verification, and microarchitecture exploration, collaborating with cross-functional teams to drive timing, power, and area

Qualifications

• Master’s degree required in Electrical/Electronics/Computer Engineering; 5–10 years of experience.
• Strong understanding of computer architecture, logic design, and VLSI design.
• Proficiency with SystemVerilog/Verilog; Python and Perl scripting.
• Experience in design verification and functional coverage preferred.

Responsibilities

• Design and implement video compression, image processing, vector computation, and flexible compute systems for AI/inference.
• Work with processor cores and memory subsystems using SystemVerilog and Verilog.
• Perform RTL synthesis, timing, area, and power optimization.
• Explore microarchitecture tradeoffs via rapid modeling with Python/Perl.
• Develop front-end methodologies and tool flows and participate in chip bring-up.

Skills

Video compression

Image processing

Vector computation

Processor cores

Memory subsystems

RTL optimization

SystemVerilog

Verilog

Python

Perl

Education

Master’s degree in Electrical Engineering/Electronics Engineering/Computer Engineering

Tools

SystemVerilog

Verilog

Python

Perl

Job description

Certified Employment Group in Santa Clara, CA is seeking a Staff ASIC/SoC Design Engineer with 5–10 years of VLSI/ASIC experience. This full-time role focuses on video compression, image processing, and edge AI applications, offering ownership of chip aspects from architecture to silicon.

You will work with SystemVerilog/Verilog, Python, and Perl across RTL design, verification, and microarchitecture exploration, collaborating with cross-functional teams to drive timing, power, and area