VLSI Design Engineer — Server/Data Center ASICs

Qualcomm; Santa Clara (CA); On-site; USD 146,000 - 218,000; Full time

Benefits offered by this job

RSU grants

Discretionary bonus

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA, seeks an experienced ASIC engineer to lead RTL design and system architecture for high-performance compute/AI oriented SoCs. You will contribute to architecture, verification, and flow improvements while collaborating across teams in a fast-paced environment.

The role requires 4+ years in ASIC design/verification, strong scripting skills, and a solid understanding of data center IPs and ML IPs. Excellent communication and teamwork are essential.

Qualifications

• Bachelor's degree in Science, Engineering, or related field plus 4+ years in ASIC design/verification.
• Master's degree in Science, Engineering, or related field with 3+ years in ASIC design/verification.
• PhD in Science, Engineering, or related field with 2+ years in ASIC design/verification.

Responsibilities

• Hands-on architecture and design of SoC per design protocol.
• Resolve architecture, design, or verification problems with minimal supervision.
• Execute design and verification strategies for ASICs, SoC, IP cores.
• Participate in design reviews and contribute analytical insights.
• Identify flow and process improvements through design techniques and automation.
• Communicate effectively within the team and with peer teams.
• Collaborate and share knowledge to achieve common goals.
• Provide feedback to process and design methodology teams.

Skills

ASIC design

RTL design

Scripting

Architecture

Verifications

Team collaboration

Education

Bachelor's degree

Master's degree

PhD

Tools

Python

SystemVerilog

C/C++

Verilog

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA, seeks an experienced ASIC engineer to lead RTL design and system architecture for high-performance compute/AI oriented SoCs. You will contribute to architecture, verification, and flow improvements while collaborating across teams in a fast-paced environment.

The role requires 4+ years in ASIC design/verification, strong scripting skills, and a solid understanding of data center IPs and ML IPs. Excellent communication and teamwork are essential.