AI Vision ASIC Design Engineer II

Ambarella; Kentucky; On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

RSU grants

Annual RSU grants

Competitive compensation

Job summary

Ambarella is seeking a qualified engineer to design and verify complex video processing hardware. You will work on RTL, front-end design methodologies, and verification efforts for edge AI accelerators and image processing subsystems.

The role requires a Master’s in electrical/electronics/computer engineering and 0–5 years of relevant experience, with strong SystemVerilog/Verilog skills and scripting experience.

Qualifications

• Master’s degree in Electrical, Electronics, or Computer Engineering.
• 0–5 years of relevant experience.
• Solid understanding of computer architecture, logic design, and VLSI design principles.
• Proficiency in SystemVerilog, Verilog, and Perl.
• Familiarity with design verification methodologies and functional coverage concepts.
• Experience with scripting languages and the ability to write assembly language programs.
• Strong communication skills and a collaborative, team-oriented mindset.

Responsibilities

• Design and implement video compression, image processing, vector processing, neural network accelerators, processor cores, and memory subsystems using Verilog and SystemVerilog.
• Perform logic design, implementation, and verification utilizing Verilog, SystemVerilog, and relevant programming and scripting languages.
• Synthesize and optimize RTL for performance, area, and power efficiency.
• Develop and enhance front-end design methodologies and tool flows.
• Contribute to chip bring-up and validation efforts.
• Analyze code and functional coverage metrics, and collaborate with the verification team to identify and address coverage gaps.

Skills

SystemVerilog

Verilog

Perl

Scripting languages

Assembly language

Analytical thinking

Communication

Education

Master’s degree in Electrical/Electronics/Computer Engineering

Tools

Design verification methodologies

Job description

Ambarella is seeking a qualified engineer to design and verify complex video processing hardware. You will work on RTL, front-end design methodologies, and verification efforts for edge AI accelerators and image processing subsystems.

The role requires a Master’s in electrical/electronics/computer engineering and 0–5 years of relevant experience, with strong SystemVerilog/Verilog skills and scripting experience.