Digital Circuit Design Engineer – DRAM Design

Anysilicon; Boise (ID); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Micron Technology in Boise, Idaho, is seeking a Design Engineer to innovate and optimize digital circuits for DRAM products. You will perform hands-on RTL design, conduct STA, and work with verification, product engineering, and test teams to ensure robust timing and performance.

The role requires a Bachelor’s degree in Electrical Engineering or equivalent, 6+ years in digital/RTL design, and proficiency with UNIX and Cadence environments.

Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 6+ years of digital/RTL circuit design experience.
• Strong RTL design, STA, and timing closure experience.
• Experience with power delivery network circuit design and optimization.
• Proficiency in UNIX and Cadence design environments.

Responsibilities

• Design and optimize RTL for DRAM‑related digital circuits and block‑level designs.
• Perform static timing analysis (STA) and drive timing closure across critical paths.
• Collaborate with verification, product engineering, test, and process teams to ensure robust designs.
• Support circuit verification, layout checks, and parasitic extraction analysis.

Skills

RTL design

STA

Timing closure

Power delivery network

UNIX

Cadence

IC Compiler

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence design environments

IC Compiler

Job description

Micron Technology is seeking a Design Engineer to innovate and optimize digital circuits for DRAM products. This role involves hands‑on RTL design and collaboration across various teams to enhance product quality and performance.

Responsibilities:

• Design and optimize RTL for DRAM‑related digital circuits and block‑level designs.
• Perform static timing analysis (STA) and drive timing closure across critical paths.
• Collaborate with verification, product engineering, test, and process teams to ensure robust designs.
• Support circuit verification, layout checks, and parasitic extraction analysis.

Qualifications:

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 6 years of experience in digital or RTL circuit design.
• Strong experience with RTL design, STA, and timing closure.
• Experience with power delivery network circuit design and optimization.
• Proficiency in UNIX and Cadence design environments.

Skills:

• Master’s degree in Electrical Engineering (preferred).
• Experience with synthesis tools and IC compilers.
• Hands‑on experience with circuit verification, layout verification, and parasitic extraction.
• Strong written and verbal communication skills.
• Ability to work independently while contributing effectively within a team.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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