Senior ASIC Analog Layout Engineer – High-Speed ICs

Anysilicon

Minneapolis (MN)

On-site

USD 110,000 - 175,000

Full time

11 days ago

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Job summary

Micron Technology in Minneapolis seeks an ASIC Analog Layout Engineer to contribute to high-speed analog and mixed-signal blocks for tester and controller IP. You will focus on the physical implementation to ensure performance and reliability across advanced processes.

You will develop custom layouts, collaborate with analog designers, perform LVS/DRC/ERC checks, optimize for parasitics and signal integrity, and contribute automation and AI-enabled tooling to improve productivity.

Qualifications

  • Bachelor's degree in Electrical Engineering or equivalent.
  • Experience with Cadence Virtuoso for analog/mixed-signal layouts.
  • Experience with LVS, DRC, ERC, and antenna rule checks.
  • Experience with semiconductor process technologies and analog layout fundamentals.
  • Master's degree preferred.
  • Experience with automation and scripting for layout tasks.

Responsibilities

  • Develop high-quality analog and mixed-signal layouts for high-speed ASICs.
  • Collaborate with analog design on manufacturable layouts.
  • Perform LVS, DRC, ERC, and antenna checks.
  • Optimize layouts for parasitics, signal integrity, EM, ESD, latch-up.
  • Contribute to layout methodologies and process improvements.
  • Develop automation and AI-enabled tooling to improve productivity.
  • Troubleshoot layout environment, CAD, and tool issues.
  • Support layout for SerDes, PLL, DLL, TX/RX, clocking circuits, and analog front-end.

Skills

Analog layout
Mixed-signal design
ASIC physical design
High-speed circuitry
Python scripting
Parasitic analysis

Education

Bachelor's degree in Electrical Engineering
Master's degree in Electrical Engineering

Tools

Cadence Virtuoso
Quantus Insight
ParagonX
PVL scripting

Job description

Micron Technology in Minneapolis seeks an ASIC Analog Layout Engineer to contribute to high-speed analog and mixed-signal blocks for tester and controller IP. You will focus on the physical implementation to ensure performance and reliability across advanced processes.

You will develop custom layouts, collaborate with analog designers, perform LVS/DRC/ERC checks, optimize for parasitics and signal integrity, and contribute automation and AI-enabled tooling to improve productivity.

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