Digital Microarchitect

Snowcap Compute Inc.; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Relocation assistance

Medical, dental, and vision

401(k)

Job summary

Snowcap Compute Inc. is seeking a senior professional to translate architecture specifications into detailed microarchitecture documents for RTL implementation. You will collaborate across architecture, RTL design, and verification teams to ensure precise interpretation and robust handoffs.

The role demands experience with silicon tapeout, end‑to‑end RTL flows, and verification. On‑site in the SF Bay Area or Jacksonville Metro, with a startup mindset and a focus on defensible engineering work.

Qualifications

• Track record of microarchitecture definition on production silicon (chips that taped out and ran workloads).
• Ability to write clear, unambiguous microarchitecture specifications for RTL teams.
• Knowledge of full RTL‑to‑GDS flow: synthesis, place and route, STA, back‑end realities.
• Able to discuss architecture with architects and RTL teams in the same week.
• Comfort writing unit tests and architectural validation code alongside specs.
• Startup mindset with ambiguity and early‑stage design work.

Responsibilities

• Translate top‑level architecture specifications into detailed microarchitecture documents.
• Define pipeline stages, datapath structures, control logic, and timing budgets for each block.
• Defend the spec during RTL handoff and revise as needed.
• Flag micro‑level issues with the architect; ensure implementation aligns with intent.
• Collaborate with RTL designers and verification engineers to land intent in implementation and testbenches.
• Optionally own design verification for specified blocks (unit tests and validation code).
• Set the standard for Snowcap microarchitecture docs.

Skills

Microarchitecture definition

RTL collaboration

Silicon tapeout experience

Job description

About the Role

Snowcap's top-level architecture defines what the chip does. RTL defines what gets built. The microarchitecture is the contract between them — and on a superconducting PCL digital chip, that contract cannot be copy-pasted from any prior program. The pipelines, datapaths, control logic, and timing budgets all have to be redrawn against a logic family whose clocking, energy, and signaling rules are not CMOS. This role owns that translation.You will take the architecture specification and produce the microarchitecture documents the RTL design team executes against. You will work directly with the Digital Architect on one side and RTL design and verification engineers on the other, in a flat, matrixed organization. You will operate fluently at both abstractions — pushing back on the architecture when the implementation will not hold, and pushing back on RTL when the spec is being interpreted past its intent.In twelve months, the microarchitecture documents you produce should be the artifact every RTL coder, verification engineer, and physical design lead points to when there is a question about how a block is supposed to work. Clean enough to implement from. Detailed enough to verify against. Defensible against physics and timing on the way down.

What You'll Own

• Translate top-level architecture specifications into detailed microarchitecture documents that RTL design engineers can implement directly, without guessing intent.
• Define pipeline stages, datapath structures, control logic, and timing budgets for each block you spec — including the parts where PCL timing assumptions diverge from CMOS.
• Own the microarchitecture-to-RTL handoff: defend the spec under review, answer implementation questions in real time, and revise the spec when implementation surfaces something the architecture missed.
• Partner with the Digital Architect to flag micro-level issues back up the stack — the architectural choices that look fine on a system diagram and break at the pipeline level.
• Work directly with RTL design engineers and design verification engineers to ensure microarchitecture intent lands intact in the implementation and the testbench.
• Optionally own or co‑own design verification for the blocks you specify — unit tests, architectural validation code, and the checks that prove the implementation matches intent.
• Set the standard for what a microarchitecture document at Snowcap looks like — unambiguous, complete, and reviewable by both the architecture side and the implementation side.

What We Need to See

• Track record of microarchitecture definition on production silicon — chips that taped out, came back, and ran the workload they were designed for. Research‑chip‑only experience does not meet this bar.
• Demonstrated ability to write clear, unambiguous microarchitecture specifications that RTL engineers can execute against without follow‑up clarification rounds.
• Solid working knowledge of the full RTL‑to‑GDS flow — synthesis, place and route, STA, and back‑end realities — and the judgment to design microarchitecture that survives the trip downstream.
• Fluency operating at both abstractions: architecture conversations with the architect, and RTL/implementation conversations with the design team, in the same week, often the same day.
• Comfort writing unit tests and architectural validation code alongside spec documents — not handing that off as someone else’s job.
• Startup‑mindset comfort with ambiguity and early‑stage design work, where the architecture above you is still being written and the RTL below you is still being staffed.

Ways to Stand Out

• Microarchitecture work at Apple, Qualcomm, NVIDIA, AMD, or comparable silicon teams in the principal engineer or microarchitect band, with shipped silicon to point to.
• Experience on non‑standard compute fabrics: dataflow architectures, near‑memory or in‑memory compute, custom ISAs, or AI inference accelerator pipelines.
• Background spanning architecture through design verification — you have done the spec, the RTL adjacent to the spec, and the validation that proves they agree.
• Experience with asynchronous, wave‑pipelined, or other non‑conventional clocking schemes — anywhere standard synchronous CMOS timing assumptions had to be re‑derived.
• Familiarity with superconducting digital logic — PCL, SFQ, AQFP, RSFQ, or related families — at any level. We do not require it; we will weight it when we find it.
• Track record of mentoring RTL designers and verification engineers into the microarchitecture mindset.
• Patents, publications, or specifications that are visible artifacts of the microarchitecture work you have done.

The Environment

Snowcap is a small, technically elite team doing chip design work that does not have a precedent. The microarchitecture conventions you would inherit at a large semiconductor company do not exist here — partly because the team is new, and partly because the underlying logic family will not tolerate all of them. You will write the conventions as you go, and the next microarchitect to join builds on what you established.
We are a flat, matrixed organization. You will work daily with the architect, RTL designers, verification engineers, physical design, and the physics team — directly, without layers. When an architectural choice and an implementation reality collide, the conversation happens in the room that day, not three reviews from now.
This role is on‑site at our San Francisco Bay Area or Jacksonville Metro location. The work is hands‑on at the spec, at the whiteboard, and in code review. If you need a mature microarchitecture organization with established review boards and templates to fill in, this is not the right fit. If you have wanted to define what those templates should look like, you are in the right place.

Why Snowcap

Snowcap Compute is building the world's first commercial superconducting digital computer. Our chips operate at 4.5 Kelvin on Josephson junction‑based PCL logic, consuming a fraction of the power of any CMOS system. We are not improving the existing paradigm — we are replacing it.
We are a technically elite, small team at the intersection of quantum physics, cryogenic engineering, and advanced semiconductor manufacturing. Every person on this team has a direct line of sight to the product. The work you do here will be visible, consequential, and unprecedented.
This is the founding microarchitecture seat. The translation layer you build between architecture and RTL becomes the standard every block, every spec, and every implementation review at Snowcap measures against.

Compensation

Full medical, dental, and vision · 401(k) · Relocation assistance available for candidates outside the area.

Base salary range is shown in USD, posted in good faith and in compliance with California pay transparency law (SB 1162). Actual offer depends on experience, skills, and location, and is exclusive of equity, bonus, and benefits. Range reflects the San Francisco Bay Area market; offers for the same role based in Jacksonville Metro, FL are typically 15–25% lower in line with local market norms.

Based in the San Francisco Bay Area or Jacksonville Metro, FL · On‑Site.