STA CAD Engineer - Timing & EDA Methodology

AMD; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD is seeking a timing analysis engineer to join the CAD Methodology team in Austin, TX. You will develop and deploy differentiating timing methodology flows for next-generation AMD designs spanning embedded to data center products.

You will evaluate EDA tools, analyze timing reports, and provide technical leadership and mentorship in a global, multi-cultural environment. A strong background in Verilog/SystemVerilog and UNIX scripting is required, with a focus on scalable automation for silicon

Qualifications

• Proficient in STA timing methods and timing closure techniques.
• Strong fundamentals in digital circuits and timing analysis.
• Familiar with Verilog/SystemVerilog and EDA toolchains.

Responsibilities

• Develop and deliver timing methodology flows for next-gen designs.
• Release high-quality flows and support design teams on issues.
• Lead evaluation of new EDA tools and features; collaborate cross-functionally.

Skills

STA timing

Timing closure

Verilog

SystemVerilog

Unix scripting

Education

Bachelor's or Master's in EE/CS

Tools

EDA tools

Python

Perl

TCL

Job description

AMD is seeking a timing analysis engineer to join the CAD Methodology team in Austin, TX. You will develop and deploy differentiating timing methodology flows for next-generation AMD designs spanning embedded to data center products.

You will evaluate EDA tools, analyze timing reports, and provide technical leadership and mentorship in a global, multi-cultural environment. A strong background in Verilog/SystemVerilog and UNIX scripting is required, with a focus on scalable automation for silicon