Sr SOC Design Verification Engineer

Mueon Corporation; Portland (OR); On-site; USD 140,000 - 190,000; Full time

Job summary

Mueon Corporation is seeking a Senior SoC Design Verification Engineer to lead verification for AI accelerators and supporting silicon. You will partner with architects, RTL designers, firmware, DFT, and post-silicon teams to build comprehensive SoC-level verification environments that ensure functional correctness across compute subsystems.

This hands-on role focuses on understanding system architecture, building reusable verification infrastructure, and driving verification from architecture

Qualifications

• 7+ years of experience verifying complex ASIC or SoC designs.
• Expert-level experience with SystemVerilog, UVM, and reusable verification methodology.
• Experience developing and maintaining large SoC verification environments, including UVM components, scoreboards, assertions, sequences, and functional coverage.
• Strong experience with gate-level simulation, SDF timing simulation, waveform analysis, regression management, and silicon correlation.
• Experience integrating commercial Verification IP (VIP) and verifying complex bus protocols.
• Experience with UVM Register Abstraction Layer (RAL) and large-scale CSR verification.
• Strong Python, Perl, Tcl, or equivalent scripting experience for automation and regression infrastructure.
• Excellent debugging, analytical, and cross-functional communication skills.

Responsibilities

• Own verification of complex SoC subsystems from architecture review through first silicon
• Develop reusable SystemVerilog/UVM verification environments for IP-, subsystem-, and SoC-level verification
• Develop verification plans, functional coverage models, scoreboards, assertions, and self-checking testbenches that enable verification closure
• Integrate and customize industry-standard Verification IP (VIP) for interfaces including AXI, APB, UCIe, PCIe, CXL, DDR, HBM, Ethernet, JTAG, and other high-speed protocols
• Lead gate-level simulation (GLS), SDF timing simulation, UPF-aware simulation, and regression debug to ensure silicon readiness
• Develop scalable UVM Register Abstraction Layer (RAL) infrastructure for CSR verification across large SoCs
• Collaborate closely with RTL, architecture, DFT, synthesis, firmware, and physical design teams to resolve functional issues and improve design quality
• Drive verification closure through functional coverage, code coverage, assertion coverage, regression health, and verification metrics
• Develop automation, scripting, AI-assisted workflows, and debug infrastructure that improve verification productivity and engineering efficiency
• Support post-silicon bring-up, hardware/software debug, and root-cause analysis by correlating simulation behavior with silicon results

Skills

SystemVerilog

UVM

Scripting

Debugging

Analytical thinking

Cross-functional communication

Education

B.S./M.S. in EE/CE/CS or equivalent

Tools

VIP

EDA tools

Job description

Company Description

Mueon Corporation is driven by the vision of "The Next Exponential", focusing on breakthrough technologies that enable the next wave of innovation in AI computing platforms. Mueon's Digital Design team develops the compute, memory, and interconnect technologies that power the next generation of AI computing platforms. The SoC Verification team works closely with architecture, RTL design, firmware, physical design, DFT, and post-silicon engineering to ensure that every subsystem functions correctly before first silicon. From IP integration through full-chip verification and silicon bring-up, the team develops scalable verification methodologies that enable reliable, high-performance SoCs and advanced chiplet-based systems.

Role Description

We're looking for a Senior SoC Design Verification Engineer to lead verification of Mueon's next-generation AI accelerators and supporting silicon. In this role, you'll partner closely with architects, RTL designers, firmware engineers, DFT engineers, and post-silicon teams to develop comprehensive SoC-level verification environments that ensure functional correctness across complex compute, memory, and die-to-die subsystems.

This is a hands-on technical role for someone who enjoys understanding complete system architecture, building reusable verification infrastructure, solving challenging gate-level debug problems, and driving verification from architecture through silicon bring-up.

Responsibilities

• Own verification of complex SoC subsystems from architecture review through first silicon


• Develop reusable SystemVerilog/UVM verification environments for IP-, subsystem-, and SoC-level verification


• Develop verification plans, functional coverage models, scoreboards, assertions, and self-checking testbenches that enable verification closure


• Integrate and customize industry-standard Verification IP (VIP) for interfaces including AXI, APB, UCIe, PCIe, CXL, DDR, HBM, Ethernet, JTAG, and other high-speed protocols


• Lead gate-level simulation (GLS), SDF timing simulation, UPF-aware simulation, and regression debug to ensure silicon readiness


• Develop scalable UVM Register Abstraction Layer (RAL) infrastructure for CSR verification across large SoCs


• Collaborate closely with RTL, architecture, DFT, synthesis, firmware, and physical design teams to resolve functional issues and improve design quality


• Drive verification closure through functional coverage, code coverage, assertion coverage, regression health, and verification metrics


• Develop automation, scripting, AI-assisted workflows, and debug infrastructure that improve verification productivity and engineering efficiency


• Support post-silicon bring-up, hardware/software debug, and root-cause analysis by correlating simulation behavior with silicon results

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience


• 7+ years of experience verifying complex ASIC or SoC designs


• Expert-level experience with SystemVerilog, UVM, and reusable verification methodology


• Experience developing and maintaining large SoC verification environments, including UVM components, scoreboards, assertions, sequences, and functional coverage


• Strong experience with gate-level simulation, SDF timing simulation, waveform analysis, regression management, and silicon correlation


• Experience integrating commercial Verification IP (VIP) and verifying complex bus protocols


• Experience with UVM Register Abstraction Layer (RAL) and large-scale CSR verification


• Experience using industry standard EDA simulation and debug tools


• Strong Python, Perl, Tcl, or equivalent scripting experience for automation and regression infrastructure


• Excellent debugging, analytical, and cross-functional communication skills