Application Specific Integrated Circuit Verification Engineer

Insight Global; Carlsbad (CA); Presencial; USD 110 000 - 160 000; Tempo integral

Resumo da oferta

Insight Global is seeking a collaborative Design Verification Engineer with 5–12 years of industry experience to help create cutting edge SoC designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success.

This role involves developing UVM-based verification environments, creating block and system level verification plans, and leading debug efforts with cross-functional

Qualificações

• Bachelor's degree in Electrical Engineering or related field is required.
• Experience developing UVM-based testbenches for ASIC or SOC verification.
• Proven ability to create test plans and verification infrastructure.
• Knowledge of verification methodologies from block to system level.

Responsabilidades

• Develop and implement UVM-based verification environments.
• Create comprehensive verification plans at block and system levels.
• Design verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams on testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Conhecimentos

UVM Based testbench development

ASIC/SOC verification experience

Test plans and verification infra

Block to system level verification

Formação académica

Bachelor's degree in Electrical Engineering

Descrição da oferta de emprego

We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. This team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

Day-to-Day

• Develop and implement Universal Verification Methodology (UVM) based verification environments.
• Create comprehensive verification plans at both block and system levels.
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

REQUIRED SKILLS AND EXPERIENCE

• Bachelor's degree in Electrical Engineering or a related field.
• UVM Based testbench development. Experience in ASIC or SOC verification.
• Demonstrated experience in developing test plans and verification infrastructure.
• Practical knowledge of verification methodologies from block level to system level.