Sr Principal Engineer -SIPI

Cadence Design Systems; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Benefits offered by this job

Paid vacation

401(k) match

Employee stock purchase plan

Medical/Dental/Vision

Job summary

Cadence Design Systems in California seeks a Sr Principal SI/PI Engineer to advance high-speed IP products. You will contribute hands-on in SI/PI design, verification, and lab measurements, providing channel models and design guidelines for customers.

The role emphasizes collaboration with R&D and customer support to optimize ASIC integration. The position requires strong SerDes/PHY expertise, 3D/2.5D extraction tool fluency, and IBIS-AMI simulations, with a focus on delivering reliable

Qualifications

• MS or PhD in Electrical Engineering (or similar degree).
• 3+ years of experience preferably working with high speed SerDes and PHYs.
• Hands-on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
• Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave.
• Experience with IBIS-AMI model simulations.
• Experience with simulation result to lab measurement correlation.
• Good understanding of PCB and FCBGA design rules and requirements.

Responsibilities

• Work on test chip package design SI/PI optimization and verification.
• Work on evaluation board design optimization for best SI/PI performance.
• Provide extracted and measured channel models for chip designers in the R&D team.
• Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
• Review customer package and board designs and simulation results; provide feedback to customers.
• Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
• Help with SI/PI related debug of test chips or customer ASICs in the lab.

Skills

SerDes experience

High-speed PHYs

Debugging

Communication skills

Lab benchmarking

Education

MS/PhD in Electrical Engineering

Tools

Sigrity Clarity/PowerSI

Ansys HFSS/SIwave

IBIS-AMI simulations

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Sr Principal Engineer This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.

Main Job Tasks and Responsibilities:

• Work on test chip package design SI/PI optimization and verification.
• Work on evaluation board design optimization for best SI/PI performance.
• Provide extracted and measured channel models for chip designers in the R&D team.
• Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
• Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
• Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
• Help with SI/PI related debug of test chips or customer ASICs in the lab.

Position Requirements:

• M.S. or Ph.D. Electrical Engineering (or similar degree)
• 3+ years of experience preferably working with high speed SerDes and PHYs
• Good understanding of high speed SerDes architecture
• Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
• Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
• Experience with IBIS-AMI model simulations
• Experience with simulation result to lab measurement correlation
• Good understanding of PCB and FCBGA design rules and requirements
• Strong debugging and problem-solving skills
• Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.