Sr. Principal Software Engineer

Cadence Design Systems, Inc.; Austin (TX); On-site; USD 140,000 - 240,000; Full time

Job summary

Cadence Design Systems, Inc. in Austin, TX seeks a highly motivated hardware engineer to join the DFT IP team.

You will design and implement DFT hardware, test fabrics, and on‑chip networks for next-generation SoCs, contributing to high-coverage, low-cost test strategies across complex designs. The role requires strong RTL/Verilog/SystemVerilog skills, UVM verification, and experience with synthesis, timing, and IP integration.

Qualifications

• Strong RTL design & verification experience in digital hardware.
• Verilog/SystemVerilog RTL coding and simulation expertise.
• Hands-on coding with SystemVerilog/Verilog; scripting in Perl/Python.
• Mastery of UVM and directed testbench verification, test planning, coverage closure.
• Knowledge of data communication across SoCs and DFT requirements.
• Experience with full-flow development, timing closure, and signoff workflows.
• Ability to lead design reviews and mentor engineers.
• Excellent cross-functional communication across locations.

Responsibilities

• Design and implement advanced DFT hardware and on-chip test networks for Next‑Gen SoCs.
• Develop test fabrics and IST/MBIST/LBIST/POST components and integrate with IP.
• Lead verification planning, ensure coverage closure, and drive quality with teams.
• Mentor engineers and drive architecture/interface decisions across RTL, verification, and physical design.
• Collaborate with CAD and software teams to ensure scalable, reusable IP.

Skills

RTL Design & Verification

Verilog/SystemVerilog

Scripting (Perl, Python)

UVM & testbench

IP integration & verification

DTF/DFT test concepts

Chips/SoC architectures

Project ownership

Debug across RTL/verify/synthesis

Tools

Xcelium

Genus

Innovus

JasperGold

Cadence signoff tools

Job description

AUSTIN

Full time

R54782

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a highly motivated hardware engineer to work with the Modus R&D engineering team in the Design-For-Test (DFT) IP business unit.

As a member of the DFT R&D team, you will design and implement advanced Design‑for‑Test (DFT) hardware, test fabrics, and on‑chip test networks used in next‑generation SoCs. You will contribute to the hardware and software development of industry‑leading test solutions such as scan compression, hierarchical test access architectures, Logic Built-In-Self-Test (LBIST), Memory Built-In-Self-Test (MBIST) , Power-On-Self-Test (POST), and In-System Test (IST). Your work will directly support high‑coverage, low‑cost test strategies across complex semiconductor designs.

Required Skills

• RTL Design & Verification

• Strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation

• Hands‑on coding and automation skills using SystemVerilog/Verilog, plus scripting with Perl and Python

• Mastery of UVM and directed testbench IP verification, including test planning, coverage closure, debug, and working with verification teams to drive quality

• Knowledge of network structures and method for communicating data across an SoC

• Full‑Flow Development & Integration

• Proven experience developing complex reusable IPs from architecture through delivery

• Strong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows

• Ability to manage internal and third‑party/services IP integrations, including requirements review, interface alignment, quality checks, and delivery tracking

• Ability to debug complex hardware issues across RTL, verification, synthesis, timing, and integration environments

• Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral

• DFT Architecture

• Deep understanding of digital design architecture, including subsystem integration, DFT, interconnects, memory‑mapped interfaces, reset/clock architecture, and low‑power design considerations

• Strong knowledge of DFT requirements for SoCs, including scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, and design‑for‑testability tradeoffs

• Knowledge of DFT IP concepts, hardware, and test network communication

• Project Ownership & Team Communication

• Experience leading design reviews, architecture reviews, microarchitecture reviews, and implementation readiness reviews

• Strong project execution and project management skills, including planning, dependency tracking, risk management, milestone ownership, and cross‑functional coordination

• Ability to mentor senior and junior engineers and provide technical leadership across teams

• Good communication skills with a development team spread across multiple locations

• Prior experience with large software development projects is highly recommended

Preferred Skills

• Experience with ISO 26262 functional safety concepts, including safety mechanisms, diagnostic coverage, safety requirements, and ASIL‑oriented design flows

• Exposure to security‑aware hardware design, including secure boot concepts, access control, lifecycle management, key handling, or secure debug

• Experience with automotive, industrial, AI, or hyperscaler‑class IP development

• Familiarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environments

• Experience driving IP maturity through reusable methodology, quality metrics, and scalable infrastructure

The annual salary range for California is $196,000 to $364,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)

Equal Employment Opportunity Policy:

Cadence is committed to equal employment opportunity throughout all levels of the organization.

• Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/equal-employment-opportunity-policy.pdf)

We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [e-mail].

Privacy Policy:

Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en_US/home/privacy/privacy-policy.html) .

E-Verify Cadence participates in the

E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/e-verify-participation-poster.pdf)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.