Sr/Principal Design Verification (DV) Engineer

MemWize, Inc; Sunnyvale, Northern (CA, KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Memwize, Inc. in Sunnyvale, CA, is seeking an experienced Design Verification Engineer to drive verification of next-generation AI/compute platforms. You will design and implement SystemVerilog/UVM testbenches, verify complex silicon, and debug issues across IP blocks and full chips.

You will collaborate with hardware and software teams, develop scalable verification methodologies, and contribute to quality through rigorous regression and coverage analysis.

Qualifications

• Experience with SystemVerilog/UVM-based verification.
• Proven debugging skills.
• Experience verifying complex AI/compute silicon.

Responsibilities

• Drive verification of next-generation AI/compute platforms.
• Develop and maintain SystemVerilog/UVM testbenches and verification environments.
• Coordinate with hardware and software teams to ensure silicon quality and coverage.

Skills

SystemVerilog/UVM

Debugging

Silicon verification

Tools

SystemVerilog

UVM

Job description

Memwize is a VC-backed, stealth-mode startup building rack-level AI inference systems .

We are seeking an experienced Design Verification Engineer to drive verification of complex next-generation AI/compute platforms. The ideal candidate will have deep expertise in SystemVerilog/UVM-based verification, strong debugging skills, and a proven track record of delivering high-quality silicon.