CPU Verification Architect — Hybrid DV (Senior/Principal)

NUVACORE, Inc.

Austin, Northern (TX, KY)

Hybrid

USD 140,000 - 230,000

Full time

2 days ago
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Job summary

NUVACORE, Inc. is seeking Verification Engineers to join the design verification (DV) team across multiple levels. You will help verify architectural correctness by driving the verification scope, creating tests, and building scalable environments.

You will work on assembly/RIS stimulus, coverage closure, and cross-functional collaboration with architects and RTL teams to fix issues and support bring-up on silicon and FPGA platforms.

Qualifications

  • Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
  • 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience on CPU or complex digital design.
  • Strong knowledge of CPU architecture, ISA like x86, ARM, or RISC-V, and architectural state.

Responsibilities

  • Plan and drive the verification scope, strategy, and test plans for architectural correctness.
  • Build, maintain, and scale verification environments with co-simulation against a gold model.
  • Create stimulus in assembly and RIS to exercise ISA and privilege transitions.
  • Define coverage space, write functional monitors, analyze metrics to close coverage.
  • Collaborate with architects and RTL teams to root-cause mismatches and support bring-up.

Skills

CPU architecture knowledge
Micro-architecture understanding
C/C++/Rust/SystemVerilog
Python scripting

Education

Bachelors in Electrical/Computer Engineering or CS

Tools

SystemVerilog
C/C++
Rust
Python

Job description

NUVACORE, Inc. is seeking Verification Engineers to join the design verification (DV) team across multiple levels. You will help verify architectural correctness by driving the verification scope, creating tests, and building scalable environments.

You will work on assembly/RIS stimulus, coverage closure, and cross-functional collaboration with architects and RTL teams to fix issues and support bring-up on silicon and FPGA platforms.

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