Design Verification Engineer 2.0

VerifAI; San Francisco (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

VerifAI in San Francisco designs verification engines that fuse RTL, ML, and AI to accelerate chip design cycles. You will contribute to developing AI-powered verification engines and work with customers to deploy scalable verification solutions.

The role emphasizes strong SystemVerilog/UVM skills, Python tooling, and experience with industry protocols, enabling rapid automation across design and verification teams.

Qualifications

• BS/MS EE/CS required or equivalent experience.
• Expertise in RTL design and verification.
• Strong knowledge of ML techniques applied to verification.
• Proficiency in SystemVerilog, UVM, and Python.

Responsibilities

• Design, develop, and accelerate VerifAI's AI Engines for chip design and verification.
• Collaborate with customers to deploy VerifAI solutions.

Skills

ML Algorithms

SystemVerilog

UVM

Python

Logic Simulation

Education

BS/MS EE/CS

Tools

AXI

PCIe

RISC-V

ARM

Job description

Design Verification Engineer 2.0 is the next generation Chip Design and Verification engineer, who is armed with deep understanding of Machine Learning Algorithms and how they can be used to accelerate Design Verification and Chip Design. The engineer, must be an expert in RTL, UVM, SVA and ML techniques to reduce the verification and chip design cycle with automation.

If you love to build great products, get in touch.

Responsibilities

Design, Develop and Accelerate VerifAI's AI Engines that power Chip Design and Verification. Work with customers to deploy VerifAI's solutions.

Qualifications

BS/MS EE/CS, ML Algorithms, System Verilog, UVM, Python, Logic Simulation experience.

Experience with industry standard protocols and Architectures, AXI, PCIE, RISCV, ARM is a big plus.

If you have built Agents for Chip Design , PD, DV, Spec-2-RTL, huge plus.