Sr Hardware Verification Engineer

Baya Systems; California (MO); On-site; USD 100,000 - 130,000; Full time

Job summary

A technology solutions firm is looking for a Senior Hardware Verification Engineer to develop test plans and implement verification strategies for complex IPs. The role involves significant collaboration with design teams to create testbenches and debug processes. Ideal candidates will have a BS/MS in Electrical Engineering or related field and over 8 years of relevant experience. Proficiency in Verilog and SystemVerilog is essential, along with the ability to work effectively on SOC-level verification projects.

Qualifications

• 8+ years of hands-on experience in block-level/IP-level/SOC-level verification.
• Proficiency in writing UVM/SystemVerilog code for test implementations.
• Familiarity with simulation and debug tools.

Responsibilities

• Collaborate with design and architecture teams to create test plans for configurable IPs.
• Implement the test plan and write UVM/SystemVerilog code.
• Define and implement configurable testbenches with software teams.
• Debug failures and close coverage in collaboration with design and DV engineers.

Skills

Verilog

SystemVerilog

Testbench development

Debugging

Education

BS/MS in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools

Job description

Job Title

Senior Hardware Verification Engineer

About the Role

We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities

• Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
• Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification
• Proficiency in Verilog, SystemVerilog
• Familiarity with industry-standard EDA tools for simulation and debug }