Space FPGA Engineering Internship - HDL Design

Roman Health Pharmacy LLC; Westminster (CO); Hybrid; USD 22,000 - 29,000; Full time

Benefits offered by this job

Mentorship program

Onsite internship

Competitive compensation

Job summary

CesiumAstro is seeking Summer 2027 FPGA development interns to help design HDL-level FPGA systems for satellite communication.

You will work with engineers on design, verification, and deployment, including high-speed interfaces, multiple clock domains, and testing with lab instruments. Excellent communication required; on-site at our Colorado facilities; current students in EE/CE with GPA 3.5+ encouraged to apply.

Qualifications

• Enrollment in BS/MS/PhD in Electrical Engineering or Computer Engineering from an accredited university.
• GPA of 3.5 or higher.
• Advanced coursework in HDL-level FPGA design.
• Hands-on FPGA project experience.
• Experience with FPGA design and verification (Verilog/VHDL, Vivado, Modelsim).
• Excellent written and verbal communication.

Responsibilities

• Develop HDL-level FPGA designs for satellite systems.
• Verify designs via simulations and tests.
• Collaborate with engineers across disciplines.
• Assist in design verification and deployment.
• Present progress to mentors and leadership.

Skills

FPGA design

Verilog/VHDL

Lab experience

Strong communication

Education

BS in Electrical or Computer Engineering

GPA 3.5+

MS/PhD coursework (optional)

Tools

Xilinx Vivado

Modelsim

HDL coder

Job description

CesiumAstro is seeking Summer 2027 FPGA development interns to help design HDL-level FPGA systems for satellite communication.

You will work with engineers on design, verification, and deployment, including high-speed interfaces, multiple clock domains, and testing with lab instruments. Excellent communication required; on-site at our Colorado facilities; current students in EE/CE with GPA 3.5+ encouraged to apply.