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CesiumAstro is seeking Summer 2027 FPGA interns to work on HDL-level FPGA systems for satellite communications. Interns collaborate with engineers across design, verification, testing, and deployment phases. Strong communication skills and hands-on lab experience are essential.
Qualified candidates are enrolled in BS/MS/PhD programs in ECE or CE, with a GPA of 3.5+, and experience in Verilog/VHDL and FPGA tools like Vivado and ModelSim.
CesiumAstro is seeking Summer 2027 FPGA interns to work on HDL-level FPGA systems for satellite communications. Interns collaborate with engineers across design, verification, testing, and deployment phases. Strong communication skills and hands-on lab experience are essential.
Qualified candidates are enrolled in BS/MS/PhD programs in ECE or CE, with a GPA of 3.5+, and experience in Verilog/VHDL and FPGA tools like Vivado and ModelSim.